You can also run out of space on the die. Silicon die sizes are limited by physics and economic considerations.
You can't put too many power hungry transistors next to each other and still be able to cool the die.
If problems are random over the area, then if you increase the die size, there are more errors per die, which drops your yield.
Why not make the DRAM out of SRAM? I think the answer is that the latency to access the DIMMs won't go down (it's dominated by the distance from the processor to the modules).
Ulrich Drepper has a good paper on the topic:
https://www.akkadia.org/drepper/cpumemory.pdf
It's a few years old, so the discussions of North/Southbridges is obsolete, but the discussion of RAM tech (p. 5) is fundamental, and hasn't changed too much (to my knowledge).