No Moore? A golden rule of microchips appears to be coming to an end(economist.com)
economist.com
No Moore? A golden rule of microchips appears to be coming to an end
http://www.economist.com/news/21589080-golden-rule-microchips-appears-be-coming-end-no-moore
23 comments
>Now that the cost of wafers are going up, making a chip that is 50% better costs 50% more money.
This is not true. In the past, process optimization was straight forward: Make smaller transistors. The free ride ended with the 130 nm node more than ten years ago. Since then, manufacturers had to introduce new features to allow them to make transistors smaller. As you also noted, this leads to higher costs, and the economics did not scale proportional to Moores law anymore.
But: This has been going on for more than a decade. The technology did not fall off a cliff and it will not do so in the near future. Even if it is not possible to make transistors smaller, it is still possible to introduce new technological features to make them better and improve their area efficiency. There are still plenty of options, even without classical scaling aka Moores Law.
TL;DR: Nothing will go poof. We are going to see a less steep gradient, but this is part of a process that started ten years ago.
This is not true. In the past, process optimization was straight forward: Make smaller transistors. The free ride ended with the 130 nm node more than ten years ago. Since then, manufacturers had to introduce new features to allow them to make transistors smaller. As you also noted, this leads to higher costs, and the economics did not scale proportional to Moores law anymore.
But: This has been going on for more than a decade. The technology did not fall off a cliff and it will not do so in the near future. Even if it is not possible to make transistors smaller, it is still possible to introduce new technological features to make them better and improve their area efficiency. There are still plenty of options, even without classical scaling aka Moores Law.
TL;DR: Nothing will go poof. We are going to see a less steep gradient, but this is part of a process that started ten years ago.
We'll see this year when the new process pricing comes out. The specific claim was not that the cost of the wafer is higher but that the $/transistor price is the same or worse for the new processes. If that holds true, then you're done with scaling by process shrinks. (Intel doesn't publish those costs of course but both Global Foundries and TSMC do)
When that minimum is reached, the economics of the 'computer' business (scare quotes because I'm specifically referring to what is known as the PC laptop/desktop business) will change fairly dramatically.
> But: This has been going on for more than a decade.
> The technology did not fall off a cliff and it will
> not do so in the near future.
When that minimum is reached, the economics of the 'computer' business (scare quotes because I'm specifically referring to what is known as the PC laptop/desktop business) will change fairly dramatically.
>That isn't a 'cliff' that is an inflection point, or perhaps a global minimum.
No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function".
There are manys way to utilize transistors more efficiently or still make them smaller while performing the same function. You have to realize that not all transistors in a chip are of minimum size due to circuit design requirements. Furthermore, only a fraction of the transistors are actually involved in performing the logic function you see from the outside. There is an increasing number of transistors spent on "housekeeping" functions such as clock distribution, power gating, bus drivers etc.
All of these can be improved by working on circuit design, improved layout software, optimzing the materials in the transistors etc. Of course this is less straightfoward than simply making the transistors smaller and therefore more expensive. Therefore we are going to see diminishing returns, but there will not be an inflexion point in the business model of the entire industriy.
No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function".
There are manys way to utilize transistors more efficiently or still make them smaller while performing the same function. You have to realize that not all transistors in a chip are of minimum size due to circuit design requirements. Furthermore, only a fraction of the transistors are actually involved in performing the logic function you see from the outside. There is an increasing number of transistors spent on "housekeeping" functions such as clock distribution, power gating, bus drivers etc.
All of these can be improved by working on circuit design, improved layout software, optimzing the materials in the transistors etc. Of course this is less straightfoward than simply making the transistors smaller and therefore more expensive. Therefore we are going to see diminishing returns, but there will not be an inflexion point in the business model of the entire industriy.
Maybe we're talking about different things.
You wrote this: "No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function"."
I claim that is does equal cost per function. Here is my reasoning on that, perhaps we can find out where we're disagreeing.
I'm going to claim that an engineering group E has a design D which they put on a process node Pn. That is a pretty easy claim since pretty much everyone who builds chips does that. :-)
I'm also going to claim that the engineering group is doing everything they can to efficiently use their transistors based on the evidence that efficiency is a key sales metric for chips today.
Then I'm going to claim that for a given design D, on a given process node Pn, you can compute an average cost per transistor for that pairing by considering the number of transistors in the design, the number of instances on a wafer, and the yield of good devices from that wafer, divided by the cost of that wafer.
Here is the assertion the article makes (and I agree with)
In the next process shrink, the cost of producing a wafer will be so high, there there will be zero change in the cost of chips produced on that process.
The engineering teams will do all they can, but the wafer costs will be so much higher that the cost per chip will either not change or go up. It will track signedness if not in magnitude this metric of 'cost per standardized transistor'. Once that is shown to be true, there will be no more investment in new processes because the economic value will not be there. And I claim that this will mean that from that point on chips will get more expensive over time with or without additional features being added.
I can't wait for the papers from the 2014 ISSCC which will tell me if I'm crazy or not :-)
You wrote this: "No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function"."
I claim that is does equal cost per function. Here is my reasoning on that, perhaps we can find out where we're disagreeing.
I'm going to claim that an engineering group E has a design D which they put on a process node Pn. That is a pretty easy claim since pretty much everyone who builds chips does that. :-)
I'm also going to claim that the engineering group is doing everything they can to efficiently use their transistors based on the evidence that efficiency is a key sales metric for chips today.
Then I'm going to claim that for a given design D, on a given process node Pn, you can compute an average cost per transistor for that pairing by considering the number of transistors in the design, the number of instances on a wafer, and the yield of good devices from that wafer, divided by the cost of that wafer.
Here is the assertion the article makes (and I agree with)
In the next process shrink, the cost of producing a wafer will be so high, there there will be zero change in the cost of chips produced on that process.
The engineering teams will do all they can, but the wafer costs will be so much higher that the cost per chip will either not change or go up. It will track signedness if not in magnitude this metric of 'cost per standardized transistor'. Once that is shown to be true, there will be no more investment in new processes because the economic value will not be there. And I claim that this will mean that from that point on chips will get more expensive over time with or without additional features being added.
I can't wait for the papers from the 2014 ISSCC which will tell me if I'm crazy or not :-)
>Now the only way to make your machine faster and cost less is to write more efficient software.
Were still a long way away from that. Switching over to SSDs represents a huge speed boost, and given how young SSDs are, I suspect that there is still room for improvement in their speed. Also, there is likely improvements to be made in CPU architecture. We are still using x86, which has been improving incrementally with backwards compatible changes since the 70s. I'm not fammiliar with CPU architecture, but I suspect this means that there is room for significant improvements in terms of per transistor efficiency with the use of a novel CPU architecture. We could also see a drop in prices due to economical, not technological forces. For example, the price of a CPU is significantly higher than the cost to produce one. This is because you are paying for the development of the CPU. Without continuing fundamental improvements, we would expect to see the cost of CPUs fall to their marginal cost as development would no longer be necessary.
Were still a long way away from that. Switching over to SSDs represents a huge speed boost, and given how young SSDs are, I suspect that there is still room for improvement in their speed. Also, there is likely improvements to be made in CPU architecture. We are still using x86, which has been improving incrementally with backwards compatible changes since the 70s. I'm not fammiliar with CPU architecture, but I suspect this means that there is room for significant improvements in terms of per transistor efficiency with the use of a novel CPU architecture. We could also see a drop in prices due to economical, not technological forces. For example, the price of a CPU is significantly higher than the cost to produce one. This is because you are paying for the development of the CPU. Without continuing fundamental improvements, we would expect to see the cost of CPUs fall to their marginal cost as development would no longer be necessary.
> I suspect this means that there is room for significant improvements in terms of per transistor efficiency with the use of a novel CPU architecture.
I seem to recall a comment a while back from an Intel chip designer guy saying that the x86 tax isn't as high as people think. Sure, the instruction set is super-crufty, but according to this guy they had found ways to implement most of the backwards compatible stuff in a way that's transistor efficient. He may have been biased, but didn't think the overhead compared to ARM was too significant.
I tried to google for the comment but couldn't find it, apologies for that. If someone with direct processor design experience would chime in that would be great.
I seem to recall a comment a while back from an Intel chip designer guy saying that the x86 tax isn't as high as people think. Sure, the instruction set is super-crufty, but according to this guy they had found ways to implement most of the backwards compatible stuff in a way that's transistor efficient. He may have been biased, but didn't think the overhead compared to ARM was too significant.
I tried to google for the comment but couldn't find it, apologies for that. If someone with direct processor design experience would chime in that would be great.
With the rise of iOS, Android, and ChromeOS which hide the CPU architecture completely from the user (especially when running Java or JavaScript applications), there are opportunities to change CPU architectures in more radical ways in the future.
But then again, the gains possible may be more limited that you suggest because the transition from x86 to x86-64 did involve a number of major efficiency gains from changing register counts and how FP calculations where done. There may not be huge efficiency gains left that are easy.
With LLVM basically being a new runtime in some cases, we can do more complex compilation strategies such as was attempted with the Itanium architecture: https://en.wikipedia.org/wiki/Very_long_instruction_word
Who knows... I'm just brainstorming today. Happy New Years!
But then again, the gains possible may be more limited that you suggest because the transition from x86 to x86-64 did involve a number of major efficiency gains from changing register counts and how FP calculations where done. There may not be huge efficiency gains left that are easy.
With LLVM basically being a new runtime in some cases, we can do more complex compilation strategies such as was attempted with the Itanium architecture: https://en.wikipedia.org/wiki/Very_long_instruction_word
Who knows... I'm just brainstorming today. Happy New Years!
The transition from x86 to x86-64 did not seem like a radical redesign of the architecture. The x86-64 bit chips are still capable of running code written for x86 chips without modification (even the 16 bit code I believe). Furthermore, the programming model (as exposed to assembly) did not seem to change between the two architectures.
As far as architectural improvements for increasing single-core performance go, we've already reached somewhat of a dead end. Intel x86 chips already do crazy things like rearranging instructions and executing 3-4 instructions at a time. With stuff like multi-core and SIMD now, we'll need compiler improvements to take advantage of the architecture improvements.
Not that compilers don't already make these optimizations. But it's pretty hard to map sequential languages like C to a many-core processor with really large SIMD units. Any abstraction that tries to make code still look sequential even if it is being executed on many cores is going to be leaky.
"is to write more efficient software. Think about that carefully. It will define success in this next decade."
But optimization is the root of all evil... or something.
But optimization is the root of all evil... or something.
Knuth's saying goes "Premature optimization is the root of all evil." Which is just another way of expressing the Unix ethic of first make it work, then make it fast.
This Moore's Law coming to an end meme reminds me of Voyager 1 leaving the solar system. You could just replace the text in the xkcd and it would be just as funny: http://xkcd.com/1189/
This is the only valid response! Classical scaling (aka Moore's law) ended with the 130nm node more than 10 years ago. The business model has been slowly changing since then.
Can you expand on this? What happened after 130nm that was different than the previous scaling?
Companies started to introduce new technological features starting with the 90nm node. This slide is a nice top level summary:
http://www.brightsideofnews.com/Data/2011_5_6/Intel-Manufact...
http://www.brightsideofnews.com/Data/2011_5_6/Intel-Manufact...
This piece from 2011 is still, to me, the definitive discussion of the end of Moore's "law" as we know it: http://herbsutter.com/welcome-to-the-jungle/
Nice piece--and, I suppose, ultimately hopeful in the sense that it suggests there are a variety of paths to increased throughput even if we're close to losing Moore's Law (at least as it comes largely from CMOS scaling). Ones does wonder though what the ultimate effect of losing the CMOS scaling lever will be on IT economics. Certainly, not all computing innovation has been about continued CMOS process shrinks. But those have been the foundation for an awful lot.
I feel like the biggest killer of Moore's Law is how much emphasis has been put on lowering/maintaining power consumption in recent years, similar to airplane performance/cost in the 1970s.
Emphasis on lower power consumption does not "kill Moore's law" or have a negative effect on computing performance. On the contrary, CPU performance has been limited by thermal output and power consumption for at least a decade and improving the power consumption will improve the performance, not the other way.
Research and development efforts have been concentrated on !/W (bang per watt) for two reasons, the other one being cooling and power supply (battery consumption) on mobile devices in particular and the other reason is being able to run at higher clocks for longer before thermal throttling kicks in.
Power consumption and thermal output are relevant for all kinds of modern computers from smartphones to servers to supercomputers. Power consumption and thermal output are related in an almost linear proportionality, twice the power consumption, twice the thermal output.
Since clock frequencies stopped going up some ten years ago, we've had a 5x to 10x increase in single core performance (in addition to multi cores) thanks to increase in power and thermal efficiency and smaller transistors. Concentrating on power consumption keeps Moore's law alive rather than kills it.
Research and development efforts have been concentrated on !/W (bang per watt) for two reasons, the other one being cooling and power supply (battery consumption) on mobile devices in particular and the other reason is being able to run at higher clocks for longer before thermal throttling kicks in.
Power consumption and thermal output are relevant for all kinds of modern computers from smartphones to servers to supercomputers. Power consumption and thermal output are related in an almost linear proportionality, twice the power consumption, twice the thermal output.
Since clock frequencies stopped going up some ten years ago, we've had a 5x to 10x increase in single core performance (in addition to multi cores) thanks to increase in power and thermal efficiency and smaller transistors. Concentrating on power consumption keeps Moore's law alive rather than kills it.
Should that matter for Moore's Law as it was defined, for number of transistors on a die? I thought that smaller transistors required less current to operate, so the incentives for lowering power consumption and upping transistor count are aligned.
The problem is that current required isn't going down as fast as transistor size, so more transistors now means more power and more cooling difficulties, or you have to work really hard on stuff like sleep modes.
Smaller size -> lower capacitance -> lower power consumption during state changes.
But smaller size -> larger leakage current -> higher baseline power consumption.
For several years we have been at the point where the curves cross and power consumption is minimal. The strategy going forward is to turn off parts of the chip when they are not in use, or to reallocate functional units to other tasks (a la Hyperthreading).
But smaller size -> larger leakage current -> higher baseline power consumption.
For several years we have been at the point where the curves cross and power consumption is minimal. The strategy going forward is to turn off parts of the chip when they are not in use, or to reallocate functional units to other tasks (a la Hyperthreading).
I'm not sure what the alternative would be. Yes, given sufficiently heroic power and cooling measures, Intel's Netburst architecture (P4) could probably have been ramped up to 10GHz or so--I think they demoed prototypes running somewhere in that range at one point. But even if you take water cooling as a given, you still have to start really focusing on power/heat at some point.
Nothing against the article because it doesn't falsify any of the conclusions, but Moore's Law is often mis-stated. Moore said that we could double the number of components in an integrated circuit every 18-24 months, nothing more. It had nothing to do with cost or power, although he did dismiss the thermal energy argument in a sentence or two in the original paper.
The interesting issue has to do with Dennard's Law for power scaling, which said that power density would remain constant as we increased component density. This isn't true any more and that's part of the reason why multicore designs are the future (2 processors at 500MHz use less than one at 1GHz for a fully parallel workload).
The interesting issue has to do with Dennard's Law for power scaling, which said that power density would remain constant as we increased component density. This isn't true any more and that's part of the reason why multicore designs are the future (2 processors at 500MHz use less than one at 1GHz for a fully parallel workload).
It did have to do with cost as well. From the original paper: "That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer."
In other words, it was the number of transistors that could economically be included in a single unit.
In other words, it was the number of transistors that could economically be included in a single unit.
Required reading for anyone who didn't see the paper last week:
The Slow Winter by James Mickens https://www.usenix.org/system/files/1309_14-17_mickens.pdf
The Slow Winter by James Mickens https://www.usenix.org/system/files/1309_14-17_mickens.pdf
Some day they are going to have to get this guy (James Mickens) on Dara O Briains science club show and/or the infinite monkey cage radio show.
I think it will come back to needing new and smarter software. Perhaps more efficient software is a better word. Magnetic disk Storage is now at silly levels, and will not hit the theoretical maximum of 20TB but even so extracting all (randomly fragmented) data off a 4tb disk will take days to weeks. So we shall head for a time not unlike the 60/70s when you arranged storage on your tape drive based on the speed of the tape passing under the head.
whatever architectures we come up with I think humanity will see increasing growth in computing power (perhaps not as insanely fast but fast) - but to use that effectively will no longer be a free ride for the developers
one last thing - More or Less podcast quoted this stat: a one billion FlOP/s chip today costs 19cents. In 1961 it did not exist but had we tried to build one machine to perform one billion operations a second it would have cost 1.1 trillion - or about the entire world GDP.
just puts Moore's law in perspective for me
whatever architectures we come up with I think humanity will see increasing growth in computing power (perhaps not as insanely fast but fast) - but to use that effectively will no longer be a free ride for the developers
one last thing - More or Less podcast quoted this stat: a one billion FlOP/s chip today costs 19cents. In 1961 it did not exist but had we tried to build one machine to perform one billion operations a second it would have cost 1.1 trillion - or about the entire world GDP.
just puts Moore's law in perspective for me
Its on life support, and pivoting to newer technologies. The turning point is towards integrated optical and quantum effects. Even switching from Silicon to Gallium Arsenide. Manufacturing processes are changing and there is no need to create anything smaller than the 10nm.
Why not Gallium Nitride?
I was quite disappointed to discover this recently. I went out and bought a new machine; I looked at all the specs, bought a sensible machine, put it together. It ran horribly. I looked everywhere... and finally checked Tom's Hardware. My processor, which had cost me $300 at the beginning of 2012, outperformed the one that I'd just bought for $200. This was... pretty much unthinkable to me. Every other two-year gap in my life was incredible; Even cheap machines were way better than their counterparts. Now I've wasted a bunch of money, a bunch of time, and gotten a worse machine.
Yes but there are a few problem that haven;t quote mapped out. While what it said there are true, it is build on the fact that previous node and growth were driven by PC market. Now that maths dont add up well because the market is shirking or not growing fast enough to keep up with the pace of node invention and wafer cost.
The more wafer used, i.e the larger scale it is produced the lower the cost per transistor. With Tablet, wearable computing and Mobile Phones, these blooming market could drive the cost economics of Moore at least to 10nm or 7nm.
I've been hearing about the end of Moore's law ever since I was in college (late 80's). There are indeed some hard limits for Silicon, but there is still a lot of space for other materials, major improvements in interconnects and better software.
Don't confuse the end of Moore's Law with the end of computer technology progress. Moore's Law is actually a pretty specific law. It says the amount of transistors in the same amount of space doubles every 2 years. We're reaching the "end of Moore's Law", because we're getting to the point where we're close to making a transistor the size of an atom, which I think is pretty much the end of "doubling the number of transistors in the same amount of space every 2 years".
That doesn't mean that after we reach this limit we won't be making quantum computers, or use other materials like graphene transistors that can probably reach TerraHertz clock speeds, which may even improve at a rate of 2x every 2 years, too. But it wouldn't be "Moore's Law".
We're also working on "brain-like" computers, but I think these and quantum computers will become "mainstream", in a general-purpose way (not just for very specific tasks), in a few decades, which should be quite a while after Moore's Law dies (in the 2020's).
So the most likely thing is that we'll use other kind of materials for the same type of "classical computers" for the next few decades, even after the end of Moore's Law, but they will improve through increasing their clock speed or through other ways, rather than getting that extra performance from adding more transistors.
That doesn't mean that after we reach this limit we won't be making quantum computers, or use other materials like graphene transistors that can probably reach TerraHertz clock speeds, which may even improve at a rate of 2x every 2 years, too. But it wouldn't be "Moore's Law".
We're also working on "brain-like" computers, but I think these and quantum computers will become "mainstream", in a general-purpose way (not just for very specific tasks), in a few decades, which should be quite a while after Moore's Law dies (in the 2020's).
So the most likely thing is that we'll use other kind of materials for the same type of "classical computers" for the next few decades, even after the end of Moore's Law, but they will improve through increasing their clock speed or through other ways, rather than getting that extra performance from adding more transistors.
Originally, it stated the number of transistors per component will double every year. If the defect density (or susceptibility to defects) goes down, it's possible to manufacture larger, more complex, components for the same price. This sort-of applies for stacked dies, with the denser interconnects and added bandwidth between layers adding to effectively higher density than single-chip (but that would be kind of cheating on Moore's Law).
A looser formulation talks about computing power. In that, we have been ahead of Moore's law with GPGPUs and vector units for quite some time. This formulation is more detached from physical process details and looks more like what the market can absorb.
In the end, what the market can absorb may prove the ultimate limit.
A looser formulation talks about computing power. In that, we have been ahead of Moore's law with GPGPUs and vector units for quite some time. This formulation is more detached from physical process details and looks more like what the market can absorb.
In the end, what the market can absorb may prove the ultimate limit.
While it's true that we're approaching the deceleration of shrinking chip size, there are still plenty of ways micro and nano computing will be optimized. Some of the more interesting developments are happening in the world of graphene R&D. This article is a little dated for such a fast-moving industry, but it's semi-relevant:
http://graphenewire.blogspot.com/2012/10/extending-memory-be...
http://graphenewire.blogspot.com/2012/10/extending-memory-be...
Graphene is interesting, but nobody in the industry believes that it will be the holy grail:
http://www.techdesignforums.com/blog/2013/12/10/graphene-get...
(This is pretty different from what academia tells you...)
http://www.techdesignforums.com/blog/2013/12/10/graphene-get...
(This is pretty different from what academia tells you...)
The critique you link to comes from an academic.
This does not mean that he is not able to present the things in proper context. However, the general situation with graphene in acedemia right now is that it is a good source of grant money. Hence you see wildy exaggerated claims of its capabilities.
3D processors
memristors
improved parallel processing
graphene
quantum
spintronics
optical
Did I miss any?
memristors
improved parallel processing
graphene
quantum
spintronics
optical
Did I miss any?
Sure, you missed all the real stuff that is going on:
- II-VI channel materials on silicon
- Finfet, Nanowire FETS (the top down variant, not the academic bottom up version.)
- RRAM (Memristors are a sub-class of these devices. Memristors mainly exist in the PR department of HP)
- TSV integration
- 3D Flash
- Memory integrated processers (see Microns Automata)
- II-VI channel materials on silicon
- Finfet, Nanowire FETS (the top down variant, not the academic bottom up version.)
- RRAM (Memristors are a sub-class of these devices. Memristors mainly exist in the PR department of HP)
- TSV integration
- 3D Flash
- Memory integrated processers (see Microns Automata)
It would be cool to write an article explaining this stuff and its expected impact in terms that most software developers could understand. I love reading this stuff but putting it into context would be useful. Your response suggests you know what you are talking about but it is fairly incomprehensible to most everyone else not deep into semiconductor technologies without just looking up each term in Wikipedia.
IEEE spectrum has a good and accurate general coverage of these topics.
http://spectrum.ieee.org/semiconductors
http://spectrum.ieee.org/semiconductors
You missed the point: it will not get cheaper, because for the first time since ages they will have to make an actual effort to make a practical use of one of those fancy technologies. Also in what way would e.g. memristors or quantum computers boost the raw processing power across all types of computational problems? It's not that simple now.
Software! Every time I poke around the code of any sufficiently complex piece of software I find myself overwhelmed with the endless levels of abstraction. One benefit of plateauing hardware performance will be the slowing of the hardware churn. As innovation slows we will hopefully converge on optimal units of computation and interfaces.
As diversity decreases it will be much easier to write libraries that talk directly to the metal, protocols that write directly to the interfaces and applications that run completely isolated at native speed.
Without the towers of abstraction it is much easier to reason about the data structures of your input and output and design optimal algorithms. If we ever do come to this point there will be a renaissance in the field of computer science field.
As diversity decreases it will be much easier to write libraries that talk directly to the metal, protocols that write directly to the interfaces and applications that run completely isolated at native speed.
Without the towers of abstraction it is much easier to reason about the data structures of your input and output and design optimal algorithms. If we ever do come to this point there will be a renaissance in the field of computer science field.
Maybe. Much of the history of computer science is the layering of abstractions. Indeed, the transition to multi-core hasn't been the disaster that many feared because various abstractions (game engines, rendering engines, Hadoop, etc.) abstract parallelism in important ways where that parallelism is actually needed.
Not being an EECS person and having only taken a couple of Intro to Circuits survey courses, can someone fill in my ignorance?
EECS people make math convenient for themselves by pretending that voltage numbers and current numbers cancel out in certain ways. Otherwise they'd have to do really messy calculus. The problem is that this convenience is only true for circuits that are up to a certain speed. Past that speed, that way of calculating and engineering circuits starts to break down. We've hit those speed limits.
The field has chosen to react by instead switching to multi-core computers. The problem from a programmer perspective is that parallelism is difficult to write for. The reason it is difficult to write for is because of mutable variables, which are common in imperative languages. So that's driving the popularity of functional languages. However, not as many people are good at functional languages, since they tend to be more mature in academic circles, less mature for industry purposes, and generally more difficult to learn for people that are more used to procedural thinking than mathematical thinking.
So, if all those premises and implications are true that would mean that maybe if the EECS people stopped pretending that EECS circuits are simple and started doing the messy calculus, maybe we could start shrinking single-core chips again. But I'm sure I've messed up some of those premises. Anyone?
EECS people make math convenient for themselves by pretending that voltage numbers and current numbers cancel out in certain ways. Otherwise they'd have to do really messy calculus. The problem is that this convenience is only true for circuits that are up to a certain speed. Past that speed, that way of calculating and engineering circuits starts to break down. We've hit those speed limits.
The field has chosen to react by instead switching to multi-core computers. The problem from a programmer perspective is that parallelism is difficult to write for. The reason it is difficult to write for is because of mutable variables, which are common in imperative languages. So that's driving the popularity of functional languages. However, not as many people are good at functional languages, since they tend to be more mature in academic circles, less mature for industry purposes, and generally more difficult to learn for people that are more used to procedural thinking than mathematical thinking.
So, if all those premises and implications are true that would mean that maybe if the EECS people stopped pretending that EECS circuits are simple and started doing the messy calculus, maybe we could start shrinking single-core chips again. But I'm sure I've messed up some of those premises. Anyone?
what do you mean by "pretending that voltage numbers and current numbers cancel out in certain ways"? The problem is certainly not that our mathematical models are insufficient. Transistor I-V characteristics have been quite complicated for several generations now. That's why circuit designers use computer simulations now, not hand-cranked calculus models.
The slow-down in processor speed despite shrinking transistor is due to physical and design limitations. For one, it used to be that you could use more transistors to build more complex pipelines, branch predictors, etc. to allow you to turn up the clock frequency. But now we've reached the point of diminishing returns on this sort of optimization. Also, increasing the frequency increases the power, which causes problems for heat dissipation and chip lifetime. So we've cut back on frequency to lower the power consumption.
The slow-down in processor speed despite shrinking transistor is due to physical and design limitations. For one, it used to be that you could use more transistors to build more complex pipelines, branch predictors, etc. to allow you to turn up the clock frequency. But now we've reached the point of diminishing returns on this sort of optimization. Also, increasing the frequency increases the power, which causes problems for heat dissipation and chip lifetime. So we've cut back on frequency to lower the power consumption.
"The field" (esp. Intel) resisted moving to multicore architectures arguably longer than they should have because of the well-known problems that major software makers (esp. desktop (Microsoft) ones) faced with moving wholesale to parallelism as a fundamental requirement. As it's turned out, the transition hasn't been as bad as it might have been for a number of reasons, but "software isn't ready" was very much a driving reason for why the P4 path was followed and (in part) for why Itanium happened.
I'm also not an EECS person, so I do not know if we are here yet, but at some point you will have to deal with quantum effects.
We already do have to worry about quantum effects. Electron tunneling is a real concern and one of the causes of chip degradation over operating lifetime. Essentially, an excited electron can jump across the transistor gate oxide and get trapped in the gate metal. If this happens enough, the threshhold voltage of the transistor increases, making it slower.
I thought Moore's law had been replaced by Amdahl's law a decade ago. Moore's law is only about the number of transistors in a chip rather than the theoretical speed improvement limits of multicore chips.
What's the law for how many stories there are per month about this obvious-for-close-to-ten-years-and-was-only-ever-a-marketing-meme-anyway "fact"?
I hope this happens soon. The ability to run current software on a 10-year-old computer (regardless of form factor) would be a great equalizer.
We were aware of this in 2005 when the Pentium 4 could not transform into another Pentium 5.
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Please don't link to articles behind paywalls.
Or a pause.
Water has been found on Mars, again?
Okay, seriously, isn't it only cared by non-technicians?
Now that the cost of wafers are going up, making a chip that is 50% better costs 50% more money. That means that this years computer is more powerful than last years computer, except it costs 15% more (chipset cost is often 1/3 the cost of parts for a machine) And if your current laptop is 'good enough' in terms of power such that you aren't willing to pay 15% more. You don't buy it. And that is what is going to really be interesting here.
The new device costs more than the old device and isn't any more capable from a feature perspective.
30 years of PC marketing "lore" goes "Poof!" Now the only way to make your machine faster and cost less is to write more efficient software. Think about that carefully. It will define success in this next decade.
[1] In the chip business a wafer start is the process of sending 1 or more wafers through the process of being made into chips. It is the smallest unit of manufacturing.