TSMC Starts $19.5B 3nm Fab Construction(tomshardware.com)
tomshardware.com
TSMC Starts $19.5B 3nm Fab Construction
https://www.tomshardware.com/news/tsmc-fab-3nm-5nm-process-intel-samsung
32 comments
Browsing WikiChip is advisable here
https://en.wikichip.org/wiki/technology_node
The short answer is that Intel is the only foundry that even tries to keep its "technology node" in step with feature size. I give them a lot of credit for it because technology node 'deflation' by their competitors has been very successful in misleading consumers and even tech-savvy people.
https://en.wikichip.org/wiki/technology_node
The short answer is that Intel is the only foundry that even tries to keep its "technology node" in step with feature size. I give them a lot of credit for it because technology node 'deflation' by their competitors has been very successful in misleading consumers and even tech-savvy people.
>The short answer is that Intel is the only foundry that even tries to keep its "technology node" in step with feature size. I give them a lot of credit for it because technology node 'deflation' by their competitors has been very successful in misleading consumers and even tech-savvy people.
1. That somewhat implies Intel is telling the truth with its features size and all others are lying, when today's features size are all pretty much marketing terms.
2. The misleading also somewhat implies Intel had the better transistor but marketing from other firms mislead consumers. Had Intel labeled their late, and not yielding latest iteration of 10nm to 7nm ( which is different to their original version of 10nm ) they would still be behind TSMC's 7nm ( Whether that is N7, N7P, or N7+ ) in both technological advance, yield and total volume output.
3. The node "deflation' started with Samsung Foundry. Morris Chang, CEO of TSMC at the time said during investor conference, they renamed their Node because their competitors ( No name given ) uses it and they were getting lots of marketing, investor and most importantly customer's pressures. If company A came out with Samsung Foundry 10nm, company B would also want to be at least 10 or 11nm. He also add the naming system before the renaming already had little relevance to the actual transistor size.
1. That somewhat implies Intel is telling the truth with its features size and all others are lying, when today's features size are all pretty much marketing terms.
2. The misleading also somewhat implies Intel had the better transistor but marketing from other firms mislead consumers. Had Intel labeled their late, and not yielding latest iteration of 10nm to 7nm ( which is different to their original version of 10nm ) they would still be behind TSMC's 7nm ( Whether that is N7, N7P, or N7+ ) in both technological advance, yield and total volume output.
3. The node "deflation' started with Samsung Foundry. Morris Chang, CEO of TSMC at the time said during investor conference, they renamed their Node because their competitors ( No name given ) uses it and they were getting lots of marketing, investor and most importantly customer's pressures. If company A came out with Samsung Foundry 10nm, company B would also want to be at least 10 or 11nm. He also add the naming system before the renaming already had little relevance to the actual transistor size.
How much is just marketing & deflation though? Presumably TSMC wouldn't put out nearly $20 billion if there wasn't some practical improvement?
Thanks for the link. Interesting in this war that they have taken the high route, whereas in the gigahertz wars, AMD had to creatively name their components so that consumers knew which Intel parts they were roughly comparable to.
It was so hard back in the late 1990s to overcome the indoctrination we all went through. I built an AMD Athlon system but it took a lot of work and self-searching to make that leap. It was like leaving a cult.
> has been very successful in misleading consumers and even tech-savvy people.
Run some common benchmarks on iPhone and on a beefy top of the line developer machine, then tell me how I am mislead.
Run some common benchmarks on iPhone and on a beefy top of the line developer machine, then tell me how I am mislead.
If you go back far enough—say to 40 or 60 no—then the measure is of the smallest resolvable feature size. What’s important, though, to feature size, is transistor & wire pitch density. It turns out that 60nm transistors & wires have a lot of ‘extra’ room between them. What’s been mostly shrinking (increasing?) is density and not absolute feature size. That’s why IBM’s smallest AFM-assembled gate is still 5 or 6 orders of magnitude smaller than (at the time) a 14nm-scale gate.
Take a look at the image in the article here which lists approximate gate and metal pitch sizes as well as showing cell layout at each process node: https://www.eetimes.com/document.asp?doc_id=1333109
Note that the structure of transistors has changed over time so that the relation of feature size to transistor capability has also changed over time; see the "Beyond the FinFET: Moving to Gate-All-Around" section here https://www.anandtech.com/show/14333/samsung-announces-3nm-g...
Note that the structure of transistors has changed over time so that the relation of feature size to transistor capability has also changed over time; see the "Beyond the FinFET: Moving to Gate-All-Around" section here https://www.anandtech.com/show/14333/samsung-announces-3nm-g...
Think of how small transistors get. Now you can pack more than double the transistors as 7nm process
Right so I was wrong here, but also the length reduction. isn’t exactly 1:1. The nm process is regarding to the certain criteria of the transistor length, could be channel length. So the width could stay the same and you wouldn’t be able to calculate exactly how much more chips you’d get unless you see the specs of how they are measured.
But if the feature size is 7nm vs 3nm, then it means I am supposed to be able to pack (7/3)^2 transistors in the same area because we're speaking length vs area here.
Is still double. Look at it one piece at a time, you shrink a square to half the size, now you store 2 in the same area.
That math you show has no basis, prob just you confusing area math instead of looking at it at a simplistic way
That math you show has no basis, prob just you confusing area math instead of looking at it at a simplistic way
That doesn't make sense, 3mm and 7mm are length measures, not areas. If they were square, then you could fit 4 3mm's in one 7mm chips area.
If you shrink the SIDE of a square to half its size, then you can fit 4 of those smaller squares in the same area...
>Can anyone explain to me what "3nm" means in practice nowadays?
In practice it means the next improvement of a full node coming from 5nm. The same rule applies to 5nm coming from 7nm. And every full node gives you anywhere from 70 to 100% density increase. TSMC normally does iteration of node, so your first version of a Full Node, whether that is 7nm, 5nm or 3nm gives you ˜80% density improvement, with subsequent node, that is 7nm+, 5nm+ or 3nm+ gives you 10 - 20% further improvement, along with performance, lower power, yield or cost etc. It is all a mix of trade offs.
The actual naming now has very little to do with any of its features size.
In practice it means the next improvement of a full node coming from 5nm. The same rule applies to 5nm coming from 7nm. And every full node gives you anywhere from 70 to 100% density increase. TSMC normally does iteration of node, so your first version of a Full Node, whether that is 7nm, 5nm or 3nm gives you ˜80% density improvement, with subsequent node, that is 7nm+, 5nm+ or 3nm+ gives you 10 - 20% further improvement, along with performance, lower power, yield or cost etc. It is all a mix of trade offs.
The actual naming now has very little to do with any of its features size.
I thought the original meaning was 'minimum design dimension'. IE, of all the dimensions in the spec, whichever is smallest. Which could be the minimum distance between components, or not.
However I understand it's now basically a marketing term, and basically doesn't correspond to anything.
However I understand it's now basically a marketing term, and basically doesn't correspond to anything.
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This is a big bet by TSMC.
If they pull it through, and they might do, they will be ahead of competition for the next decade.
I wonder what Intel's response to this will be. I haven't heard any news about them getting in the 3nm game within the next 2 years.
Do we know the story of what happened in the Intel 10nm debacle? I know that they went from being a generation ahead of everyone to a generation behind TSMC, but that seems like a bigger misstep than just fumbling a single node.
I've heard rumors that 10nm was late and management at Intel put a lot of pressure on the process teams, which led to the "old guard" quitting and the younger generation left fumbling with unusable yields.
But they're only rumors - it's entirely possible that's not the case.
But they're only rumors - it's entirely possible that's not the case.
The only thing I have to go on is the fact that the semiconductor rumor mill absolutely called this one.
Years ago, when intel was publicly announcing that 10nm would ship in a few months, the rumor mill said that not only would it not ship in a few months, it would not ship at all for the foreseeable future, up to the point of missing the entire 10nm node. That's exactly what happened.
The scenario you described would be 100% consistent with those observations. I still look forward to the inside scoop because, in accordance with your suspicions, I suspect there's a juicy case study in there about self-deluded "beatings will continue until morale improves" style management felling an industry titan, or at least stumbling it badly.
Years ago, when intel was publicly announcing that 10nm would ship in a few months, the rumor mill said that not only would it not ship in a few months, it would not ship at all for the foreseeable future, up to the point of missing the entire 10nm node. That's exactly what happened.
The scenario you described would be 100% consistent with those observations. I still look forward to the inside scoop because, in accordance with your suspicions, I suspect there's a juicy case study in there about self-deluded "beatings will continue until morale improves" style management felling an industry titan, or at least stumbling it badly.
If TSMC does this and Intel doesn't then by proxy AMD will absolutely destroy Intel on every metric.
I believe that they were going to skip 10 nm and go to 7 nm, although they are already on the 10 nm process at certain foundries.
10nm++++++++ of course.
They're still on 14 nm ++
What about Cannon Lake and Ice Lake then? Both of those lines are supposed to be 10 nm.
Cannon Lake had a fumbled release last year and Ice Lake processors started shipping with some newer computers last month.
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture...
https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)
Cannon Lake had a fumbled release last year and Ice Lake processors started shipping with some newer computers last month.
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture...
https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)
You are correct. Intel is on 14nm+++ for Desktop/Server/Mobile but there are some Ice lake mobile chips at 10nm.
Meanwhile Intel is working on 14++++++++nm technology that improves performance by 0.000000001%
This will be an easy game for AMD and TSMC...
This will be an easy game for AMD and TSMC...
So, what is it actually supposed to mean? And how does 3nm correspond to the real, physical layout of the chips?
EDIT: Thanks for all the answers, I'll be sure to read through the links. Very interesting stuff :)