PicoEVB – Artix-7 FPGA board with M.2 interface(picoevb.com)
picoevb.com
PicoEVB – Artix-7 FPGA board with M.2 interface
https://picoevb.com/
8 comments
I hate to rain on the open source FPGA parade, but I do a lot of hobby FPGA stuff using both closed (Quartus, ISE) and open (yosys, arachne) source, and when I have the choice, I go closed source every time I have the chance.
It’s not the the open source doesn’t work, it usually does, and the small size of it is really nice, it’s that it doesn’t come close in terms of debugging functionality when things go wrong.
My current workflow is to always develop using Quartus first, and only when things work perfectly I move it over to ICE40.
But even then I sometimes have an identical mid sized RTL design that works perfectly on my small Altera and Xilinx boards, and it just doesn’t work on my ICE40 board.
How do I debug this?
There is no easy signaltap or chipscope route. I just have to guess and hope for the best.
Unfortunately, what also doesn’t help is that all those cheaper Lattice FPGAs are woefully outdated. And their newer ones aren’t supported by open source tools yet.
I hope things improve fast, but for now, I’d advise hobbyists who are getting their toes in the water to use closed sourced tools.
It’s not the the open source doesn’t work, it usually does, and the small size of it is really nice, it’s that it doesn’t come close in terms of debugging functionality when things go wrong.
My current workflow is to always develop using Quartus first, and only when things work perfectly I move it over to ICE40.
But even then I sometimes have an identical mid sized RTL design that works perfectly on my small Altera and Xilinx boards, and it just doesn’t work on my ICE40 board.
How do I debug this?
There is no easy signaltap or chipscope route. I just have to guess and hope for the best.
Unfortunately, what also doesn’t help is that all those cheaper Lattice FPGAs are woefully outdated. And their newer ones aren’t supported by open source tools yet.
I hope things improve fast, but for now, I’d advise hobbyists who are getting their toes in the water to use closed sourced tools.
> How do I debug this?
We (or more likely, Clifford Wolf) writes the code to do it. Maybe not today, but proprietary software wasn't replaced by open source software in a day.
I'm not saying that yosys is a replacement for Vivado, it's obviously not, but here we have a nice Artix-based board and with not too much effort we could also offer a completely free, easy to use toolchain for it, perhaps not one which does everything, but definitely enough to download designs, compile a bitstream and program it onto the board.
Instead we have this huge barrier to entry - download 40GB [sic] of proprietary crap and register for a time-limited account which is tied to the particular chip you're using.
We (or more likely, Clifford Wolf) writes the code to do it. Maybe not today, but proprietary software wasn't replaced by open source software in a day.
I'm not saying that yosys is a replacement for Vivado, it's obviously not, but here we have a nice Artix-based board and with not too much effort we could also offer a completely free, easy to use toolchain for it, perhaps not one which does everything, but definitely enough to download designs, compile a bitstream and program it onto the board.
Instead we have this huge barrier to entry - download 40GB [sic] of proprietary crap and register for a time-limited account which is tied to the particular chip you're using.
> I'm not saying that yosys is a replacement for Vivado
Actually, you kinda did:
>>> Please let's kill off Vivado once and for all. [...] There are open source tools for programming FPGAs, and they are really great too: https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...
Actually, you kinda did:
>>> Please let's kill off Vivado once and for all. [...] There are open source tools for programming FPGAs, and they are really great too: https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...
"with not too much effort"
Right, and my truck runs on dreams and starlight.
Right, and my truck runs on dreams and starlight.
Lattice should embrace Project IceStorm and give Clifford millions of dollars and unlimited support, these open-source tools really set them apart in the FPGA world.
I really don't understand why the smaller companies such as Lattice wouldn't do this. It gives them an instant advantage, for next to no money in the grand scheme of things.
For people starting out, yes you can and should absolutely avoid things like Vivado if possible, because they are otherwise big, inscrutable pains in the ass, and you will hate them. Also the devices are relatively expensive comparatively. You'll be simulating a lot anyway.
But, Vivado does a lot of very valuable things in practice that will take a lot of time to really replace properly, if you're doing serious FPGA work for Xilinx systems. Or even if you're doing semi-serious work. A working flow is one thing, killing it off is a much harder challenge.
Even for Lattice FPGAs, IceStorm does not match e.g. Lattice iCEcube2 in terms of features or functionality (timing analysis reports, power estimation, floorplan and pinout UXs, very standard clock synthesis and constraint options, etc etc.) But it's way better at the things it actually does, admittedly. Despite that, I still find myself reaching for iCEcube2, even if my actual flow is IceStorm. These are all fixable and you can live without them, but that's for a simple EDA tool on the simplest/cheapest consumer FPGA you can buy, with a limited technology library and hard IP.
The ongoing move to use tools like VPR however will polish a lot of that off (power/timing/clock constraint synthesis). XRay will benefit from that. The rest is going to be a lot of IP cores, simulation models, middleware, and software tooling, and that's what's needed to really kill off something like Vivado.
Debugging tools are probably the most important middleware in particular, and they are sorely lacking.
Personally at least, I will say Yosys is IMO the nicest synthesis tool there is. So, if you are OK with Verilog, the FOSS community does have some best-in-class tools already. :)
But, Vivado does a lot of very valuable things in practice that will take a lot of time to really replace properly, if you're doing serious FPGA work for Xilinx systems. Or even if you're doing semi-serious work. A working flow is one thing, killing it off is a much harder challenge.
Even for Lattice FPGAs, IceStorm does not match e.g. Lattice iCEcube2 in terms of features or functionality (timing analysis reports, power estimation, floorplan and pinout UXs, very standard clock synthesis and constraint options, etc etc.) But it's way better at the things it actually does, admittedly. Despite that, I still find myself reaching for iCEcube2, even if my actual flow is IceStorm. These are all fixable and you can live without them, but that's for a simple EDA tool on the simplest/cheapest consumer FPGA you can buy, with a limited technology library and hard IP.
The ongoing move to use tools like VPR however will polish a lot of that off (power/timing/clock constraint synthesis). XRay will benefit from that. The rest is going to be a lot of IP cores, simulation models, middleware, and software tooling, and that's what's needed to really kill off something like Vivado.
Debugging tools are probably the most important middleware in particular, and they are sorely lacking.
Personally at least, I will say Yosys is IMO the nicest synthesis tool there is. So, if you are OK with Verilog, the FOSS community does have some best-in-class tools already. :)
For people starting out, yes you can and should absolutely avoid things like Vivado if possible
This must be the weekly "Give beginners terrible advice" thread.
This must be the weekly "Give beginners terrible advice" thread.
>The Virtex 7 series has been reverse engineered
I might be missing something, but is that Virtex 7 or Artix 7 ? From the project page, it looks like Artix, and that's great since many hobbyist level entry boards use Artix 7, like Arty, Basys and Nexys (at the upper end)
I might be missing something, but is that Virtex 7 or Artix 7 ? From the project page, it looks like Artix, and that's great since many hobbyist level entry boards use Artix 7, like Arty, Basys and Nexys (at the upper end)
AIUI the whole 7-series has been reverse engineered.
Are you kidding or have you never used other EDA tools? Vivado is a breath of fresh air compared to many synthesis / PnR tools, including the defacto industry standard ones. It's exceptionally intuitive compared to others. Perhaps you're referring to the predecessor ISE?
He probably hasn't used it for a couple of years. Vivado was pretty awful when it was first introduced, but they've made a ton of progress.
It's fine now, or at least as 'fine' as FPGA tools ever get. Much better than ISE ever was. In any case, there is currently no alternative if you're looking at using a Xilinx part that is supported only by Vivado and not ISE.
It's fine now, or at least as 'fine' as FPGA tools ever get. Much better than ISE ever was. In any case, there is currently no alternative if you're looking at using a Xilinx part that is supported only by Vivado and not ISE.
Lots actually, all the way back to Altera's Max Plus+II in the mid 1990s.
Have You used non fpga EDA, like ASIC tools? Compared to those Vivado is amazing. There is clearly a concerted effort to continually improve usability and performance. Check out the YouTube videos released with each version outlining the major changes and you'll be pleasantly surprised.
Nice. Adding this to my watch list. Another project I've been looking into is the snickerdoodle.
https://www.crowdsupply.com/krtkl/snickerdoodle
https://www.crowdsupply.com/krtkl/snickerdoodle
It's been taking quite a long time to deliver many of the parts, unfortunately. I was watching it for a time but a lot of newer boards seem to be coming out and at this point unless you need the extended addons, you may be able to get more for less.
The snickerdoodle is probably better if you want to do a lot of electronic breakout. Otherwise, for straight FPGA work, at this rate, the new Avnet Ultra96 simply looks like a superior base platform in most respects, and will be shipping in volume quite soon.
The snickerdoodle is probably better if you want to do a lot of electronic breakout. Otherwise, for straight FPGA work, at this rate, the new Avnet Ultra96 simply looks like a superior base platform in most respects, and will be shipping in volume quite soon.
The Snickerdoodle got a lot of attention for its price point (which turned out to be unrealistically low... I commend them for following through though). It's an odd platform. They were going for an ecosystem of carrier boards, but ended up with 0.050" pitch connectors. Which are good if you've got flying leads, but I can't see myself using a Zynq for that kind of work. The mating connectors are ~$7 in small quantities which is comparable to the smaller, tighter pitch connectors other dev boards use, so there isn't really a cost savings if you build your own plug-in boards. It might even cost more for wide I/O in terms of connectors and board space.
You're right that technology has continued to march along. $250 for a Zynq Ultrascale is very tempting, but I have enough dev boards collecting dust...
You're right that technology has continued to march along. $250 for a Zynq Ultrascale is very tempting, but I have enough dev boards collecting dust...
This is by far the cheapest board to test out a PCIe FPGA design BTW. It’s so much cheaper than other PCIe boards it’s worth it to buy a used laptop on ebay with M.2 and you’d still save money :o
With how often laptops have a single wireless m.2 slot (always?) I've always thought it odd they chose that as the m.2 slot to use.
Agreed, why not attach it to the internal USB bus? Maybe it’s a sourcing / business deal thing. I’m theorizing most laptop manufacturers have made a deal with m.2 pcie wifi producers and not the usb WiFi producers.
I feel like this would be better suited to those with NUCs or other small PC dev workstations, rather than laptops. Otherwise, wouldn't you have IO cables hanging out of your lappy?
The digital I/O allows to implement custom wireless signaling (SDR). To avoid crappy cables hanging out of the notebook, what about a custom jack connector as a frontend shield? ;)
How useful would this be for a total beginner who wants to start messing around with and learning FPGAs? Looks super skookum.
It would be pretty great, but I've actually never been able to get Vivado to work, despite having a license for the given board, I activate it and install everything, and sometimes it seems like it activates for some other system in the family instead of what I have, and I'm left with the cutest little silicon brick.
I got a couple iCE40 boards and fired up yosys/icestorm (never touched the [more feature complete, I'm sure] proprietary toolchain for these), instant satisfaction, and I was able to do exactly what I wanted (and on any host CPU architecture or operating system I wanted). The only limitations were a lack of big IO, rather small memory, limited system size.
Frankly I think Lattice should just hire a couple people endorsed by Clifford Wolf (since I know Clifford is a very busy dude) to package up his brilliant toolchain with a bow, fill in the desired analytical features, and ship it as the official iCE40 toolchain. Maybe they could try to get something similar going for their larger FPGAs (which are unrelated to the iCE40, which they got as part of an acquisition) as well.
I got a couple iCE40 boards and fired up yosys/icestorm (never touched the [more feature complete, I'm sure] proprietary toolchain for these), instant satisfaction, and I was able to do exactly what I wanted (and on any host CPU architecture or operating system I wanted). The only limitations were a lack of big IO, rather small memory, limited system size.
Frankly I think Lattice should just hire a couple people endorsed by Clifford Wolf (since I know Clifford is a very busy dude) to package up his brilliant toolchain with a bow, fill in the desired analytical features, and ship it as the official iCE40 toolchain. Maybe they could try to get something similar going for their larger FPGAs (which are unrelated to the iCE40, which they got as part of an acquisition) as well.
Do they make any iCE40 boards like the PicoEVB? I wouldn't mind something that didn't sit inside an M.2 slot inside a laptop for my tinkering, but I do think it is an intriguing form factor. I know zero about any of these toolchains.
Would it be fast enough for mining?
There are open source tools for programming FPGAs, and they are really great too: https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...
The Virtex 7 series has been reverse engineered, but we're not quite in the situation where you can use the open source tools yet: https://github.com/SymbiFlow/prjxray