I find your company fascinating, having also worked on chips (and chip dev tooling) for much of my career.
> But they want to work on chips, not devtools!
I have long had a gut feeling that there's an entire industry of frustrating tools specifically to keep that industry alive. I once was shocked to learn that my company had bought licenses for a tool specifically to combine multiple IP-XACT specs into one... basically just parsing several XML files and combining their data! Outrageous.
RE orchestration: It's easy-ish now since it sounds like you're starting out with (free) open source tools, but once you start looking at things like license fair-share, you might find yourself starting to build yet-another-Slurm/LSF.
Any reason for buck2 vs bazel? Bazel seems more active (O(thousands) questions on StackOverflow for Bazel vs O(hundreds) for buck).
I started my career off in the chip design world, where 100% line, branch, FSM transition, functional group, and toggle (i.e. individual bits in a bus switching 0 -> 1 _and_ 1 -> 0) was "table stakes". There are a lot of comments in here saying that achieving 100% coverage would be expensive - and they're right. The majority of headcount in modern chip design houses is taken up by verification engineers, whose sole job is to architect, implement and maintain a minimal test corpus that achieves that high bar. The cost of failure is simply too high to omit this step.
It was unsettling to me after moving to a SWE job where coverage was kind of... not as important.
The functionality of the F-91W is simple enough that I don't think a CPU would even be needed. Probably the digital parts of this chip are just state machines. That being said, the left half of the die shot looks like some kind of gigantic ROM, which could either be used by a CPU (as static program memory) or just transition logic/data for any generic state machine(s).
Verilog came out in 1984, but its use for synthesis (i.e. actually compiling text into circuits) was not popularized until much later, after correctness bugs in synthesizers and various other advancements in design tooling came around. It might have been used as a simulation/verification language for the digital portions of this chip.
The "Silicon" part of Silicon Valley is still very much relevant. Intel, AMD, nVidia, etc. all have major presences down there. There's also a multi-billion dollar industry supporting silicon design shops in various ways, and they're all in SV too.
Gate-level simulation (even zero-delay, let's not mention delay-aware or even power-aware) for a modern-sized CPU takes weeks just to run through some basic liveliness checks. See [1] for just a taste of gate-level simulation trickiness:
Is this true? I'm pretty sure that most of the regex engines I've used (grep, ripgrep, re2, hyperscan) use Thompson's construction or at least some NFA-based algorithm (not necessarily Thomopson's; Glushkov automata in particular are used by hyperscan).
Based purely on the name and a super quick scroll through the github page, it's probably the Lattice ice-series of chips, even more probably the ice40. There are a couple boards with ice40 chips out there that you can use fully OSS tooling for from synthesis to PnR to programming.
(Digital) chip designer here: this is super cool. What tech node are you targeting? Have you checked out any of the free open-source tools and PDK from Skywater, Google, eFabless and co?
The $1k figure quoted by OP is not indicative of the average price of licenses in my experience. There are plenty of tools that are $15k+ in the EDA world, and various engineers in chip design orgs are always battling about who gets to use them and when. There are whole teams in big SoC design shops dedicated to managing and procuring licenses.
I was pretty far removed from the license procurement and budgeting aspect of my last chip design job, but IIRC we were in the multi-millions per year in various EDA tool licenses. That figure may or may not have included IP licenses for pre-designed off-the-shelf subsystems.
I almost got kicked out because I "looked like" someone who had vandalized something or other the day before. They pulled me out of class, called me names, made me sit in their little sad office (thus missing more class) and tried to get me to write a written confession. I refused and they said they would "prosecute me to the full extent of the law". The next day I was exonerated with no explanation given.
The two fully-grown adults who ran the security office were former police; judging by the 20+ department badges proudly displayed on their back wall, it looks like they'd been kicked out of every department. One wonders why!
That makes sense. It kind of seems like the new program will be sort of a mish-mash of ChE, systems eng, and ECE (i.e. what it takes to actually run a fab).
In fairness, I think overall there are no curricula specifically about how to run a factory. Most engineering degrees focus on design and theory rather than industrialization. For example, there are no classes on how to run datacenters for computer science majors.
Skimmed the article; what's the difference between this program and what's already taught in electrical and computer engineering classes? I studied ECE for my BS and MS and there were already a couple of chip design-related courses: digital design, VLSI, FPGA, semiconductor physics, IC fabrication. I guess more specialized coursework on verification or manufacturing would have been nice, but I don't think that would warrant a whole new academic program.
edit: forgot to mention that I worked as a chip designer for many years right out of school.
I've worked with Samsung Semiconductor as a partner/customer and it did seem to me from the outside that there was a culture of not admitting mistakes/failings, and poor communication between different parts of the company (i.e. foundry to silicon engineering). Granted, you could say the same thing re: communication about many large companies -- I'm sure the same phenomenon occurs at Intel or IBM (back before they went fabless). Things may have been different on software teams vs. silicon/hardware teams.
TIL about JDK's vector API. That's awesome; I mostly work in the C and C++ space and have learned to embrace the gigantic ifdef's for various arch-specific vectorized instructions.
Verilog, VHDL, and SystemVerilog are supported by Vivado. A small subset of C++ is supported through Vivado's high level synthesis compiler, which transforms some C++ code into Verilog. RTL stands for register-transfer level, which is a general layer of abstraction; one uses a hardware description language such as Verilog to describe RTL designs. The analogy of Verilog with RTL is "Verilog is to RTL, as Haskell is to functional programming".
Of course "the same HDL" is a reductive statement, since components like high-speed IO, or even clock gates are not easily portable between FPGA vendors or foundries. But the user-land Verilog/VHDL code that describes how your custom thing "works" is generally portable.
I'd like to know more about the PCIe Gen2. From your comment it sounds like the root port is capable of Gen2x2, or is it 2x Gen2x1 ports? If I wanted to attach a PCIe accelerator card with a standard PCIe connector, is there some kind of adapter cable I would need to buy?
> But they want to work on chips, not devtools!
I have long had a gut feeling that there's an entire industry of frustrating tools specifically to keep that industry alive. I once was shocked to learn that my company had bought licenses for a tool specifically to combine multiple IP-XACT specs into one... basically just parsing several XML files and combining their data! Outrageous.
RE orchestration: It's easy-ish now since it sounds like you're starting out with (free) open source tools, but once you start looking at things like license fair-share, you might find yourself starting to build yet-another-Slurm/LSF.
Any reason for buck2 vs bazel? Bazel seems more active (O(thousands) questions on StackOverflow for Bazel vs O(hundreds) for buck).