Awaitless: Ipython and REPL and Coroutines – Suffering
github.com3 pointsby gsmecher1 comments
from more_itertools import take
def drv_clock():
while True:
yield "1b1"
yield "1b0"
for x in take(10, drv_clock()):
print(x)
I also hope this is coming anyway (see e.g.: KiCad nipping at Altium's heels, and Verilator's recent progress). There is just so much more to do, though...