This is useless without any data: "big difference between the generated verilog". You would need an actual case study to confidently state these and as pointed out with programming languages this is difficult to do.
That is very dangerous not verifying, in some means, that each of the formats are functionally identical. One could skip the Cosimulation in MyHDL as well. This has nothing to do with the so called abstraction level of chisel.
Converting to yet another format can be a pain and potentially dangerous, if you are creating a commercial ASIC you need to guarantee each of these formats/representations are equivalent, if there is a discrepancy between the generated C++ and generated Verilog for implementation - oh boy.
This is ridiculous, you can create cycle accurate (and bit accurate) descriptions in MyHDL. Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to Verilog, and perform a Cosimulation. One can even Cosimulation with the back-annotated layout netlist and verify - yes cycle accurate.