Exactly why we zero asic is making Platypus devices open bitstream and all tooling foss from day one...to protect the world against future evil/dumb version of ourselves.
Of course we don't have silicon yet...so nobody here cares. I think a lot of people forget that Xilinx spent $10B+ develop their awesome devices. I figure we can do it with 1/10th of that.;-)
Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86.
Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.
We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)
I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC.
Weird title, makes it seem like a reveleation. There have been numerous Viking treasures discovered in Sweden with traces from the the Islamic world and it's well known that they were all over England as well.
The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000).
We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...
First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic.
The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the first standard is to be the lowest common denominator of FPGAs that anyone can implement, else the threshold is too high. Kind of like RV32I.
Oh no, we have lost another giant! Very few people in the world know the gratitude she is owed. I doubt Nvidia and the other fabless companies would exist without her contribution. I met her through DARPA in 2018 [ref] and I later reached out for advice when I started a company in 2020. She was kind and generous with her time in all of our interactions. Beyond her technical prowess, she really understood people. The community/collabroation aprpach she used to launch the VLSI revolution in the 1970's are worth studying.
Makefiles can work for simple builds. Logik being Python based can do so much more: automated metrics gathering, conditional flows, parallel execution, error handling, dependency management
Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn't really been done before.
case #1. If you truly have something custom IP, we could save time/effort by only chipletizing that part rather than working on the while SoC. The design and verification is an exponential function with respect to complexity(#blocks, die size). We can turn RTL into a 2mm x 2mm brick fairly easily.It would require a fab shuttle/mask sets though.
case #2. Depends on huw much power goes to the PL vs other functions. For PL dominated FPGAs that you fill up to the brim, our only value would be to help like in case #1. For multi chip solutions (FPGA + CPU) with small amounts of PL, a corretly designed small catalog of off the shelf chiplet approach wins.
The swappable nature of the chiplet bricks was meant to convey that they are the equivalent of toy plastic blocks. We didn't disclose the standard yet, this will be coming soon.
No my bad for not being clear. If all you want is a bunch of LUTs then the high end fpga is the right answer. FPGA today is a lot of other things besides PL (serdes, cpu, DSP, ML, DDR IF...) and some of those features are only available on the bigger FPGAs. FPGA portfolios have man gaps due to the enormous costs of designing each one of those FPGA products.