Open Source FPGA Expansion Card for the Apple II(wiki.reactivemicro.com)
wiki.reactivemicro.com
Open Source FPGA Expansion Card for the Apple II
https://wiki.reactivemicro.com/A2FPGA
8 comments
If you program the FPGA with an Apple ][ emulator, can we call it a HyperCard?
If you are as curious as I were what the card looks like, then have a look at this:
https://github.com/a2fpga/a2fpga_core/blob/main/boards/a2n20...
I always find it impressive how integrated our electronics have become and how few components are required to achieve what would have taken large, crowded PCBs in the past.
https://github.com/a2fpga/a2fpga_core/blob/main/boards/a2n20...
I always find it impressive how integrated our electronics have become and how few components are required to achieve what would have taken large, crowded PCBs in the past.
Project co-creator here - that's actually the V1 board, the V2 board is here https://github.com/a2fpga/a2fpga_core/blob/main/boards/a2n20... and uses a slightly larger CPLD (complex programmable logic device) which is what's used to map and level shift the 5V signals from the Apple II bus to the 3.3V pins on the FPGA module. We use the Sipeed Tang Nano 20K FPGA module for the FPGA. Using a pre-built module like this is a great accelerator in this type of project because a lot of the more complicated things to get right, like the power supplies or the length of the traces for the HDMI connector, are done for you.
Very cool project - I'd be all over this if I was lucky enough to own an Apple II!
(I think there's a typo in the credits section of the github Readme: you have alanswx listed as Alex Steremberg instead of Alan?)
(I think there's a typo in the credits section of the github Readme: you have alanswx listed as Alex Steremberg instead of Alan?)
Yup, definitely Alan not Alex! Alan has been the person who has brought a lot of attention to the Apple II core in the Mister FPGA platform.
Quick question: my ROM03 IIgs has a Transwarp GS, SCSI card-hard disk and GGlabs 8MB RAM card. Think this would work with that configuration, or would it likely have conflicts?
I have the exact same setup except for the SCSI card and it works with that. The issue will be if the SCSI card is in one of the slots that has been virtualized on the FPGA (4 and 7 by default), in which case there will be address range conflicts. For example, if the SCSI card is in slot 7, then it will conflict with the SuperSprite functionality which uses the address range for Slot 7. There is a "No-Sprite" version of the firmware which disables the SuperSprite or you can move the SCSI card to Slot 3 and put the A2FPGA in Slot 7. ROM03 GS units have the necessary address line signals that the A2FPGA needs on all the slots whereas previous models of the GS only had those on Slot 3.
I think it's in 6 (or was it 3?), but I'll verify. Thanks for the info!
Yep. I've been looking at an old arcade board's design for fun lately, and it's a lot of giant (for today's standards) DIP chips that are just flip-flops, and gates, or gates, which modern cheap FPGAs have by the tens or hundreds of thousands in them.
YouTube interview with creators: https://www.youtube.com/watch?v=gJXZZJZc5gI
Great to see the Sipeed Tang Nano modules being used - they are based on a Gowin FPGA chip and the dev modules (with HDMI and a stack of GPIO pins broken out) cost peanuts on aliexpress compared to equivalent FPGAs from more popular vendors. The vendor IDE is usable and open source tools are improving. Exciting times for embedded hobbyists.
This is fantastic. I once dreamed of making a generic interface card that could be programmed at will, using, say, a raspberry pi. However, a look through the timing diagrams in Sather shows surprisingly tiny latencies between the address and r/w signals hitting the bus, and the memory value needing to be presented. I concluded that an fpga would probably be required. Always fun when you can wait a few years and someone smarter than you builds the thing you imagined!
Project co-creator here - This was something I'd wanted to do since I first started playing with FPGAs 20 years ago but the idea was resurrected during the pandemic. It's definitely easier with an FPGA but there are other projects that interface an ESP32 or RP2040 to the Apple II bus. The FPGA approach allows you to architect your logic in ways that are much closer aligned to the original hardware design and in many cases, you can directly translate Sather's logic diagrams to Verilog code. BTW, Sather's book has recently been reissued: https://www.callapple.org/books-3/understanding-the-apple-ii...
GitHub repo here - https://github.com/a2fpga/a2fpga_core/
720x480 is not 720p, that's 480p (assuming progressive scan and not interlaced).
Good catch, that's a mistake that's now been corrected, it's definitely 480p. The Github page (https://github.com/a2fpga/a2fpga_core) had it correctly.
once again i regret my decision to get an apple //c for my collection rather than the more expandable apple ][ or //e. in my defense, it just looks so cute!