Verilog for all proposed RISC-V bitmanip instructions(github.com)
github.com
Verilog for all proposed RISC-V bitmanip instructions
https://github.com/riscv/riscv-bitmanip/tree/master/verilog
0 comments
—
https://github.com/riscv/riscv-bitmanip/tree/master/verilog
—