Intel vs. NuFlare in multi-beam race(semiengineering.com)
semiengineering.com
Intel vs. NuFlare in multi-beam race
https://semiengineering.com/next-gen-mask-writer-race-begins/
1 comments
Why is mask write time such a big deal? They mention 24 hours as a general upper limit, but given that silicon iterations take several weeks, it doesn't seem like a major factor.
Probably because the cost of the mask writers is so huge. As the article says, only 10 - 12 mask writers sales are expected in 2017. My guess is these machines will run 24/7, practically. The more masks it can make, the more units over which you can amortize the capital costs.
Depending on the layout complexity, mask write times for EUV masks can take many days with a single beam mask writing tool. Considering that even with EUV dozens of masks are needed for a mask set for a 7nm product, this would result in a few months of total processing time, of course multiple mask writers are typically used in manufacturing sets. The time issue can be mitigated but not at unlimited cost.
Educated guess, one die will have many layers, requiring many masks for all the layers
You are correct. Total # of masks for a modern IC can be 30-50 or possibly more. And with double and even quad patterning on the critical layers, that's 2 or 4 masks for a single layer.
Dies are one dimensional, making multi dimensional dies is the next challenge in IC manufacturing.
Today we do use 2.5D transistors AKA FinFets but that's still as single layer.
Multiple masks are used however as creating the feature size expected today with the wavelengths we have requires multiple patterning which means multiple masks are used.
14nm today still uses the same 193nm lithography from 65nm if not earlier, the only way to create features which are actually smaller than the wavelength of the light is by using multiple hard mask and resist layers.
Today we do use 2.5D transistors AKA FinFets but that's still as single layer.
Multiple masks are used however as creating the feature size expected today with the wavelengths we have requires multiple patterning which means multiple masks are used.
14nm today still uses the same 193nm lithography from 65nm if not earlier, the only way to create features which are actually smaller than the wavelength of the light is by using multiple hard mask and resist layers.
Ah, they don't use masks for the metal and via layers?
Lots of layers, yield < 100%, multiple teams / designs in flight.
In any case,
> how long it takes to write a mask is the principal determination of both the cost of the mask and also the yield of the mask
In any case,
> how long it takes to write a mask is the principal determination of both the cost of the mask and also the yield of the mask
The mask isn't independant of the silicon this isn't something that is put between the silicon and the lightsource like in a slide projector (that would be the master but today the masters are no longer physical objects).
Masks are "written" on the silicon in layers and then etched out, most IC manufacturing processes use multi-patterning which means that multiple masks are printed on the silicon, exposed and then etched out.
The longer it takes to make an IC the lower the yields which bring up costs considerably.
Edit: well I was partially incorrect Photomasks are still used maskless manufacturing aka MAGIC isn’t there yet a combination of hard masks which are printed on the silicon and Photomasks are used to create the pattern.
Intel currently uses quadruple patterning so 4 masks in total are needed to create the final pattern.
There is a bit more complexity for 2.5 designs such as wall masking but this is beyond me.
Masks are "written" on the silicon in layers and then etched out, most IC manufacturing processes use multi-patterning which means that multiple masks are printed on the silicon, exposed and then etched out.
The longer it takes to make an IC the lower the yields which bring up costs considerably.
Edit: well I was partially incorrect Photomasks are still used maskless manufacturing aka MAGIC isn’t there yet a combination of hard masks which are printed on the silicon and Photomasks are used to create the pattern.
Intel currently uses quadruple patterning so 4 masks in total are needed to create the final pattern.
There is a bit more complexity for 2.5 designs such as wall masking but this is beyond me.
"Edit: well I was partially incorrect"
No, you were completely incorrect TBH.
No, you were completely incorrect TBH.