> Also I still haven’t figured out how to combine a mechanical and digital solution. Like I want light switches that match my server state for my lights. If I change the switch via my phone, I want the switches to change as well so that the physical switch is always the true state of the light.
For the lights that I want to "keep mechanically in sync" I replaced the switches with buttons and used a re-flashed (ESPhome) sonoff-mini which conveniently has a button input for the relay.
Everything is synchronized no matter the operating interface.
> The hardware industry can't benefit from rapid iteration because every iteration costs a mask set.
Before tapeout there are steps which could benefit I suppose. But as a functional-programming n00b I don't see how that could be the solution. I would argue that improving place and route algorithms to the point that deploying to a (large) FPGA is almost as quick as compiling software would be a huge step forward.
VHDL springs off of ADA, so I wouldn't say it was specifically developed.
Anyway, ADA and VHDL are strongly typed, which incidentally works well with critical applications development such as hardware design.
You have high-level-synthesis tools on many FPGA vendors tools, using C/C++ or even Python for hardware description. I personally don't think they are superior than typical HDLs, the thing that makes the difference is to think about the circuit you ought to describe, the language you use then is not as important IMHO.
HDL (hardware description languages - Verilog and VHDL the most representative ones) do actually work like that.
They give you access to structural descriptions for bitwise control, but also and mostly behavioural descriptions which allows hierarchies of modules (the blocks you described) and abstraction up to anywhere basically. This last part is generally referred to as RTL (register transfer level) design.
To make a circuit from this RTL description you usually need more steps: synthesis (where RTL gets "compiled" into the actual gates and flops to be used) and implementation (where the logic gates of the previous step are actually translated in the "fabric" you have available - FPGA logic blocks, a foundry's standard cell library ...).
> One of the biggest problems with being indispensable and announcing that you feel stuck, is that the business will take steps to get you even more stuck, through more money, shinier titles and stock options.
This worries me, as I'm experiencing it right at this time. No idea how to get unstuck either.
The only linked source to this is express.co.uk, and even that doesn't direct to a related article, but the homepage...
It seems that a bunch of theories and research ideas from 6 years ago has been thrown in just for the sake of making a "news article", it would be good to have some sources for this.
It makes me glad to read such success stories as I can partially relate.
I have been working on 2/3 side projects for almost three years now, and my partner realised soon how much happier I am when working on my startups and ideas...but mistrust in myself is still too strong.
Also I only have experience with "manufacture-centered" businesses, maybe the risk with a Saas feels different?
Doing VHDL designs for a living here, using SystemVerilog once in a while when absolutely required. Take my words with a good pinch of salt!
SV is anyway a hardware description language, so you still think and code in terms of modules and signals (wires) to be connected. But if you want to create structures that use variables and have a more "procedural" style, I find that SV is more agile than VHDL for this specific purpose.
If you want real high level languages for hardware there are tools that provide synthesis from C/C++, Python and more software oriented languages.
Indeed VHDL is supposedly based as much as possible on Ada syntax. Naturally you would have several differences due to the purpose of the languages, but they are _very_ similar IMO