CXL-Based Direct Accessible, High-Performance Memory Disaggregation Framework [pdf](camel.kaist.ac.kr)

2 ポイント投稿者 pbalcer4 年前1 コメント

camel.kaist.ac.kr

CXL-Based Direct Accessible, High-Performance Memory Disaggregation Framework [pdf]

https://camel.kaist.ac.kr/public/camel-cxl-memory-pooling.pdf

1 コメント

Worth clicking for just the image of the memory-board they've built. Unlike most pcb's, it's stark & open, hardly a passive component on it. Really wild to see so much open boardspace. They have 8 dimms here. I suspect it's basically just an FPGA acting as a CXL memory controller, but perhaps there's more.

They compare themselves versus RDMA over Infiniband (56Gbps) which makes sense as it's the competitor. They claim a 2-4x advantage basically, which is great. On the other hand, this is pretty much memory plugged in to a PC, so yeah, one would hope it would be significantly faster to reach. Once more advanced CXL topologies start emerging, it will be interesting to revisit.

Medium term, I imagine we'll be seeing variants of stuff like this with HBM stacks onboard. See the recent UCI chiplets alliance, with AMD, Intel, TSMC, Samsung, others. To tie it back to my first comment, this would just be a modest modern microminaturization of this wide open sparsely-populated huge PCB... just put this whole thing on chip. A very large (capacity), very small (footprint) memory module.

It's unsurprising that this company is claiming some patents over this technology even in the press brief. Hopefully the core ideas of CXL are allowed to germinate & grow, without the ecosystem immediately becoming IP overencumbered.