Resets NEED to be asynchronous assertion, what if the clock distribution logic is messed up, or just isn't running yet on power-up? De-assertion does need to be synchronized, though. Method is left as an exercise for the reader.
Also, aside from the latency added, dual-flop synchronizers are pretty good probabilistically for uniformly distributed single-bit random events, but they aren't guaranteed. For mesochronous signals they can actually make things worse, and for periodic signals or buses, there are much better methods.
But those issues usually come up in advanced designs with high-speed data inputs (PCIe or Ethernet) or other reasons to NEED multiple clocks. For beginners, the important thing to remember is that resets assert asynchronously and de-assert synchronously.
Also, aside from the latency added, dual-flop synchronizers are pretty good probabilistically for uniformly distributed single-bit random events, but they aren't guaranteed. For mesochronous signals they can actually make things worse, and for periodic signals or buses, there are much better methods.
But those issues usually come up in advanced designs with high-speed data inputs (PCIe or Ethernet) or other reasons to NEED multiple clocks. For beginners, the important thing to remember is that resets assert asynchronously and de-assert synchronously.