On FPGAs there is a third way for a register to get new values: FPGA configuration. When FPGA is re/configured initial values specified (like in previous post) will be set as value of FF.
FWIW, Systems Engineer is the designation for entry level engineers at Infosys. Since it's a service company with engineers working on all sorts of techs it doesn't really make sense calling those positions Java Dev or Web Dev or whatever.
BTW This Xilinx white paper is a good read about FPGA resets. https://www.xilinx.com/support/documentation/white_papers/wp...