Yes, this infinite loop solver would take longer than the universe's age to print all possible configurations of this 4k monitor, but it would take a finite amount of time as opposed to infinite. (Provided that the integer n is big enough as a arbitrary precision fixed point unsigned integer)
Both aren't that reproducible, I keep running into sha256 hash nondeterminism when upgrading packages on nixos from source after not updating for a while and guix may be better at this.
I changed the printf line of code to this (printf("%2x", integer);) to make it a pseudorandom number generator and made a post about it https://news.ycombinator.com/item?id=39462913 (10 Lines of code 3.4 bits of noise per byte weak pseudo random number generator)
I compiled it, ran ./vitalixprng &> output.txt and then ran Detect It Easy's entropy measuring tool on output.txt to give me around 3.41 bits of randomness per 8 bits.
It outputs 2 hex characters (hex character = half byte = 4 bits) per clock cycle.
It gives out pseudorandom output that looks like this:
Are you making a pipelined FPGA architecture or a systolic array?
How would you improve my FPGA? I have two directions that I could take my FPGA architecture such as adding analog Logic Blocks and adding beamforming LUT interconnect.
Can you explain how you would go about getting an MVP manufactured?
I raised $372.03 for my FPGA chip on my profile and I've only sketched out a rough mock prototype of what I want the architecture to be.
So far, it works with any amount of silicon defects, can be up to the size of a silicon wafer, and the larger it is, the more it can reconfigure itself in parallel, which is directly proportional to its size growth.
What percentage of problems would benefit from parallel reconfiguration? I'm raising money for an FPGA in my profile where programs aren't bottlenecked in FPGA reconfiguration but instead are reconfigured in parallel.