One thing I forget to mention in the article is that the RISC-V Vector Extension doesn't really have to be used to compute long vectors. In theory you could set a vector length of 4 and depending on the architecture you'd still get good performance. But in that case you'd also lose some of the power efficiency advantages I talk about...
Sigh, I really hope you're wrong. I can't stand the new keyboards (sticking to a last-gen Macbook Air) but the only thing worse than those keyboards are the official iPad keyboard folios from Apple. I'd seriously rather use the onscreen keyboard...
On the other hand, if we had to rely on keyboard cases, there might be better options than what we have today - e.g. I've heard a lot of good about this Razer mechanical iPad Pro keyboard although it's obviously very bulky: https://www.macworld.com/article/3115739/input-devices/razer...
By coincidence I started a new blog a few days ago and my first article is about the SIMD Instructions Considered Harmful post from a power efficiency perspective... maybe I should post it separately on HN? :)
I think I'm kinda explaining how it's similar (and different) to what modern GPUs do but I'm not sure I understand what you mean by "wouldn't we be able to process 16 of them at the same time" - do you mean a throughput of 16/clock, or just that 16 are "in flight" through the pipeline with a throughput of 4/clock?
I'm not sure I'm clear enough about it for those without a GPU HW background. If it's not clear I'm happy to write down a more detailed explanation here!
I completely agree in principle (some applications are good fit for traditional long vector processing, but it's a terrible fit for others).
However the RISC-V Vector Extensions basically let you use the processor in "SIMD mode" by setting the vector length to a small value. It will depend on the processor architecture whether a vector length of e.g. 4 is efficient or not, but I expect for many implementations it will be relatively efficient (and you can definitely just use it as a "wider GPR" if you want to).
The only catch at the ISA level is it costs an instruction to change the vector size. So if you keep swiching between e.g. 128-bit and 512-bit instructions at a very fine granularity, that might add overhead... I'm not sure that's a very common case though?
One thing I forget to mention in the article is that the RISC-V Vector Extension doesn't really have to be used to compute long vectors. In theory you could set a vector length of 4 and depending on the architecture you'd still get good performance. But in that case you'd also lose some of the power efficiency advantages I talk about...