Why is Ivy Bridge so hot?(overclockers.com)
overclockers.com
Why is Ivy Bridge so hot?
http://www.overclockers.com/ivy-bridge-temperatures
23 comments
The takeaway I got from this article is that if I use solder to attach my heatsink to the spreader on my Core i5 2500K instead of thermal paste, I could get a big jump in heat conductivity. Now if only I had the tools to create a solder point that large...
I haven't looked at the flux-less bonding patents mentioned in the article, so I'm not sure just how difficult it would be to create that bond without flux, but otherwise it shouldn't be that difficult in principle to spread a thin layer of solder paste, then attach the heatsink and heat them to reflow and form the bond. That's basically how the QFN[1] and other 'no-leads' ICs are mounted.
There are 2 big problems though: You've got a huge overhang area, so if you do use flux, it's not going to be able to escape, and will stay as voids in the joint. But if you don't, you'll have to find some other way to replicate the cleaning and oxide stripping behaviour in order to get the solder to bond properly. Chemical cleaning and then storage/soldering in an inert atmosphere might help, but I don't know.
Secondly, and perhaps more importantly, it's really quite hard to reflow (heat to melting point) the solder layer attached to your big heatsink, without bringing the whole assembly up to that temperature (what with the whole point of the heatsink being to get heat away from there as fast as possible). And if you do that, even if you don't fry the chip straight away, you've now got all that thermal energy stored in the large mass of the heatsink to dissipate. And it has to be done relatively evenly to avoid mechanical stress on the joint due to material expansion/contraction.
Actually yeah, having thought it through, it is going to be pretty tricky :)
[1] https://en.wikipedia.org/wiki/Quad-flat_no-leads_package
There are 2 big problems though: You've got a huge overhang area, so if you do use flux, it's not going to be able to escape, and will stay as voids in the joint. But if you don't, you'll have to find some other way to replicate the cleaning and oxide stripping behaviour in order to get the solder to bond properly. Chemical cleaning and then storage/soldering in an inert atmosphere might help, but I don't know.
Secondly, and perhaps more importantly, it's really quite hard to reflow (heat to melting point) the solder layer attached to your big heatsink, without bringing the whole assembly up to that temperature (what with the whole point of the heatsink being to get heat away from there as fast as possible). And if you do that, even if you don't fry the chip straight away, you've now got all that thermal energy stored in the large mass of the heatsink to dissipate. And it has to be done relatively evenly to avoid mechanical stress on the joint due to material expansion/contraction.
Actually yeah, having thought it through, it is going to be pretty tricky :)
[1] https://en.wikipedia.org/wiki/Quad-flat_no-leads_package
Thankfully, someone already sells that. http://indigo-xtreme.com/
The '>20 W/mK' claimed by this method, while a lot better than the 5 W/mK of regular TIM, is still a fair way off the 80 W/mK that the article claimed for a soldered solution.
Does anyone know if any commercial CPUs have been packaged factory fused to a heatsink?
There are 200W Power 7 CPUs, and they don't have to worry about aftermarket cooling like high end x86 CPU manufacturers do. It seems like it could really make sense there.
There are 200W Power 7 CPUs, and they don't have to worry about aftermarket cooling like high end x86 CPU manufacturers do. It seems like it could really make sense there.
Why do that when you can take the IHS off and attach the heatsink directly to the silicon? You know, like everyone does on their laptops...
Because a solder layer would have much higher thermal transfer rate per area than thermal paste. And the IHS is bigger than the die, resulting in better cooling (because there is more 'bandwidth' (=area) at the point where TIM is used).. which was pretty much explained in the article.
The heat sink could easily replace the role of the heat spreader if it was soldered on. It's much bigger. I could definitely see processors moving to an integrated and standardized heat sink.
That doesn't make sense - TIM is used to fill the gaps where the copper and silicon don't have direct contact (that's why you use as little of it as possible), not as a heatspreader itself. A direct heatsink-silicon contact will almost always be better for thermal conductivity...
The logical next step, sadly unexplored, would have surely been to do some testing without the IHS?
E: turns out it doesn't really help[0], though that doesn't mean it wouldn't have been better if soldered.
0. http://www.overclock.net/t/1249419/pcevaluation-intel-i7-377...
E: turns out it doesn't really help[0], though that doesn't mean it wouldn't have been better if soldered.
0. http://www.overclock.net/t/1249419/pcevaluation-intel-i7-377...
It doesn't make sense to me that Intel would do this just to save a nickel, unless solder is way more costly than I imagine. I'd like to know if some other aspect of production makes paste more desirable.
The only Ivy Bridge chips that are out are engineering samples. It's good that people are bringing it up, but this is likely just a beta thing. Maybe they wanted to be able to remove the IHS...or maybe they didn't want people to know the final overclocked performance characteristics for some reason.
What does engineering sample mean? I could go to Microcenter right now and buy a Core i5 3570K right now if I wanted to. Are they selling engineering samples? That seems like a somewhat shady move.
The first Ivy Bridge consumer chips are just hitting retailers today (NewEgg just put them on sale ten hours ago). All of the experiments done so far have been on review chips sent out some weeks ago.
It means pre-production, or beta. No, Microcenter is not selling engineering samples..the production chips _just_ became available. I suspect we'll see a new round of testing today/tomorrow that'll hopefully shed more light on this.
https://en.wikipedia.org/wiki/Engineering_sample
https://en.wikipedia.org/wiki/Engineering_sample
Why not? The harm is to heat dissipation at high clock rates and voltages -- basically to overclockers. The targeted clocks at the performance points they are aiming at don't have any trouble staying in reasonable temperature ranges, so why bother?
Lots of this is market based, not technical. The only competitors to Ivy Bridge are from AMD, and frankly don't compete well. There's simply no pressure to produce a "pull out all the stops" max performance chip. They have a comfortable margin even with comparatively poor heat sink designs, so they might as well save the nickel.
Lots of this is market based, not technical. The only competitors to Ivy Bridge are from AMD, and frankly don't compete well. There's simply no pressure to produce a "pull out all the stops" max performance chip. They have a comfortable margin even with comparatively poor heat sink designs, so they might as well save the nickel.
I could also be that (if true) using the paste could meet their engineering/temperature requirements and using solder to conduct the heat was overkill. In this case, the only ones that would feel the pinch would be those that overclocked the chips.
The biggest problem I'd imagine with the direct-soldered die is that it's a much more rigid interface, which means any localised heating is going to put much more mechanical strain on the die.
In contrast, the TIM is much more flexible, and the reduced heat transfer might actually work in its favour, by buffering sudden thermal spikes to reduce the cross-die gradient (and thus stress).
In contrast, the TIM is much more flexible, and the reduced heat transfer might actually work in its favour, by buffering sudden thermal spikes to reduce the cross-die gradient (and thus stress).
Could it be that Intel is making current generation of Ivy Bridge less over-clockable, so when the next generation is due, they just change the thermal conductivity of it, and over-clock it a bit more and call it a new chip?
No, the next generation is a "tock" in Intel parlance, which is a whole new microarchitecture.
Thanks for mentioning intel tick-tock. I had not heard that before.
http://www.intel.com/content/www/us/en/silicon-innovations/i...
http://www.intel.com/content/www/us/en/silicon-innovations/i...