Conditional instructions in the ARM1 processor, reverse engineered(righto.com)
righto.com
Conditional instructions in the ARM1 processor, reverse engineered
http://www.righto.com/2016/01/conditional-instructions-in-arm1.html?m=1
3 comments
Conditional instructions had been removed for one reason, not related to the register encoding: they were at odds with the OoO execution.
Yes, as the designers of the RISC-V ISA (an unrelated recently-designed ISA) explain (http://riscv.org/spec/riscv-spec-v2.0.pdf page 17):
"Both conditional move and predicated instructions add complexity to out-of-order microarchitectures, adding an implicit third source operand due to the need to copy the original value of the destination architectural register into the renamed destination physical register if the predicate is false."
But removing predicated instructions on 64-bit ARM freed four bits on the encoding of every instruction. What's the obvious use for four extra instruction bits? Adding one bit to each register field, thus doubling the number of registers. That is, my guess is that having twice the number of ISA-visible registers was a consequence of removing the predication bits, not its cause.
"Both conditional move and predicated instructions add complexity to out-of-order microarchitectures, adding an implicit third source operand due to the need to copy the original value of the destination architectural register into the renamed destination physical register if the predicate is false."
But removing predicated instructions on 64-bit ARM freed four bits on the encoding of every instruction. What's the obvious use for four extra instruction bits? Adding one bit to each register field, thus doubling the number of registers. That is, my guess is that having twice the number of ISA-visible registers was a consequence of removing the predication bits, not its cause.
I didn't program the ARM1, but I programmed the ARM2 extensively in assembler. The ARM2 was very similar to the ARM1 (it had a multiply instruction and a co-processor interface).
The conditional instructions were one of the things that made the ARM really fun to program in assembler. The others being that lovely array of 15 general purpose registers, and knowing that each instruction took 1 cycle (4 for memory accesses) meant that you could optimize the code by looking at it instead of having to run it!
Unfortunately conditional instructions and superscalar / out of order execution don't mix, so they can actually slow your code down now-a-days if you are running on a modern ARM processor.
The conditional instructions were one of the things that made the ARM really fun to program in assembler. The others being that lovely array of 15 general purpose registers, and knowing that each instruction took 1 cycle (4 for memory accesses) meant that you could optimize the code by looking at it instead of having to run it!
Unfortunately conditional instructions and superscalar / out of order execution don't mix, so they can actually slow your code down now-a-days if you are running on a modern ARM processor.
IIRC, that's why they were removed in ARMv8.
The more you know, the more you know you don't know. Interesting article, even if I only really understood the title.
At the same time, the 64-bit ISA doubled the number of registers, which probably was made possible by the instruction encoding bits freed by removing this conditional instructions feature.