If you prefer the term person to avoid confusion, fine by me. But then also don't use the term "experimenting on humans", because the meaning of that is experimenting on persons against their will.
There is nothing extra magical about conception that makes the creation of a human (or a person if you prefer that), all of the DNA already existed before and nothing that defines a person is yet present.
Testing on early stage embryos is a thing yes. They have no brain, no heartbeat, feel no pain. Yes, they could potentially develop into a human being, but I wouldn't call it a live human yet. I understand your repulsion, but to other people it's no different than testing on sperm, eggs or other human tissues. And as the other guy said, these were discarded embryos from IVF, they would never become humans.
Here in Belgium it's the other way around. we've had IPv6 for over 10 years for basically all home internet, but mobile is still ipv4 only. Not sure why since it's all the same companies.
It is far from solved in IC, synthesis tools sometimes still do really stupid things and there's still quite a lot of hand-holding required to get to a working chip.
Real hardware has clock trees. Wouldn't all (most?) problems with delta cycles go away if the HDL understood the concept of clocks and clock balancing?
In a way is further away, but in another way it's actually closer to how real hardware works: Clock (and reset) trees are real physical things which exist on all digital chips.
Is it really if you restrict yourself to sensible design practices? You generally want to simulate simple clocked Logic with a predefined clock, most of the time anything else is a mistake or bad design. So just if rising edge clk next_state <= fn(previous_state, input) . It seems to me VHDL and verilog are simply at the wrong abstraction level and by that they make simulation needlessly complicated and design easy to do wrong. To me it seems that if they had the concept of clocks instead none of this would be necessary and many bugs avoided (but I'm no expert on simulator design, so I might be missing something...)
I'm not sure if you are trolling. 99.999% of digital design is "if rising edge clk new_state <= fn(old_state, input)", with an (a)sync reset. The language should make that the default and simple to do, and anything else out of the ordinary hard. Now it's more the other way around.
The real question is, why do we even need this? Why don't VHDL and Verilog just simulate what hardware does? Real hardware doesn't have any delta cycles or determinism issues due to scheduling. Same thing with sensitivity lists (yes we have */all now so that's basically solved), but why design it so that it's easy to shoot in your own foot?
I think we'll be soon at the point where articles are written by asking AI to extend a three point bullet list to 30 pages, and read by asking AI to summarize articles into a three point bullet list.
Another possible benefit I've heard of is it can stop some kinds of voter intimidation:
Someone gets hand of an empty ballot, they fill in the ballot and give it to you and tell you to come back with another empty ballot. Rinse and repeat. Of course, with today's smartphones there are simpler ways to do this. Also moot if you can vote by mail, which is why voting by mail is a really bad idea.