I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable.
In both tools most of my design spins take <3 minutes.
If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively.
I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.
With the Xilinx ISE toolset I am currently using (which Xilinx is deprecating in favor of the new Vivado toolset) it parallelizes/multithreads poorly. I understand that the place and route algorithm is based upon simulated annealing, in which you make small random perturbations to the current layout configuration, measure whether it is better or worse, and sometimes retain the new configuration, and sometimes roll back. This gradually evolves the system to a configuration which maximizes some objective function, avoiding getting stuck in a local maximum. It has traditionally been a challenge to parallelize this sequential algorithm through design partitioning because of placement and routing interactions between the partitions.
In some flows you can do a coarse floorplan of your design and route the submodules separately and then stitch them together. I imagine this is how the very largest devices are implemented in manageable design iteration times.
I don't usually worry about that, though. Since my design is just so many replicated tiles, I tend to do design iterations of 4- or 16-processor elements to test the impact on clock period / timing slack. That usually takes 2-3 minutes per design spin. Only once in a while do I place and route the whole chip to confirm some change doesn't impact timing closure.
pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB physical RAM on a Core i7-4960HQ rMBP.
In both tools most of my design spins take <3 minutes.
If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively.
I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.