Die Shots of the Raspberry Pi RP2040(twitter.com)
twitter.com
Die Shots of the Raspberry Pi RP2040
https://twitter.com/johndmcmaster/status/1355092011829719046
15 comments
Microcontrollers being on larger processes like this is nothing new. As you mention, it's a way to keep using older fabs, but that's not the only reason.
40nm offers tons of performance for microcontrollers and the die area can still be reasonably small. You tend to want to have lots of variants of microcontrollers for different applications, so mask costs matter. And you tend not to want exotic, very low core voltages and do want high voltage tolerances and strong drivers on the IOs, which mean relatively big geometry-- no matter what your minimum feature size is.
Also, sleep power consumption is important, so low leakage is nice, which is easier to get on large geometry.
40nm offers tons of performance for microcontrollers and the die area can still be reasonably small. You tend to want to have lots of variants of microcontrollers for different applications, so mask costs matter. And you tend not to want exotic, very low core voltages and do want high voltage tolerances and strong drivers on the IOs, which mean relatively big geometry-- no matter what your minimum feature size is.
Also, sleep power consumption is important, so low leakage is nice, which is easier to get on large geometry.
40nm is a quite recent move for MCUs, and the mainstream majority can still be anywhere in between 90nm, and 180nm.
Only very few, top of the line MCUs ventured to 40nm, like ESP32 which had no other option because of WiFi eating gates, or ST's MCUs with 3D accelerator on board.
Problem for MCUs is that MCU specific features start to cost too much more in IP, design time, yields, and fab service cost below 90nm. Things like embedded flash, per-model mask memory, SRAM, non-CMOS cells, RF, and other analogue circuitry.
Below 28nm conventional eFlash, and many other things stop scaling, and only proprietary solutions are on the table at the moment.
Only very few, top of the line MCUs ventured to 40nm, like ESP32 which had no other option because of WiFi eating gates, or ST's MCUs with 3D accelerator on board.
Problem for MCUs is that MCU specific features start to cost too much more in IP, design time, yields, and fab service cost below 90nm. Things like embedded flash, per-model mask memory, SRAM, non-CMOS cells, RF, and other analogue circuitry.
Below 28nm conventional eFlash, and many other things stop scaling, and only proprietary solutions are on the table at the moment.
BayBal, since you're an expert in Semi, I wonder if you can fill in the blanks?
EbenUpton(Raspberry Pi's CEO) , on Twitter:"We get ~20k die per wafer""
A Tsmc 40nm wafer costs about $2300.
How much do you estimate the full chip manufacturing cost for this would be ?
I wonder, because Eben Upton talked about "business model hacking" in regards to this chip, so they may want to do some interesting stuff in the mcu market.
EbenUpton(Raspberry Pi's CEO) , on Twitter:"We get ~20k die per wafer""
A Tsmc 40nm wafer costs about $2300.
How much do you estimate the full chip manufacturing cost for this would be ?
I wonder, because Eben Upton talked about "business model hacking" in regards to this chip, so they may want to do some interesting stuff in the mcu market.
> BayBal, since you're an expert in Semi, I wonder if you can fill in the blanks?
An expert? Ahahh, I never even had formal education in the field, just been trying to enter it, and start studies in it for a few years.
My only real experience with ICs was with a company developing a fancy synchronous rectifier chip what was capable of doing few more tricks with the output waveform besides rectification, and that was mostly just hanging around, and doing complete trivialities like routing, or minimal layout wiggling. I was more useful there as a coffee porter.
> How much do you estimate the full chip manufacturing cost for this would be ?
I don't know how many wafers they buy. I don't know whether they ordered masks from TSMC, or somebody else. I don't know how short they want lead times to be. I don't know if they want to have any device inspection provided. I don't know if they have any agreements on repeated runs, or a flexible capacity purchase. I don't know if they order test, and packaging from TSMC.
From a man who was on Allwinner's original A10 chip team, I heard that the most bare bones 65nm run without mask cost, inspection, or packaging was possible at 1k wafers at $2400-$2500 in 2013-2014 by paying cash 1y in advance.
Today, I'm not even sure if clients are even allowed to, or can order masks on the side these days for latest processes.
The universal advice I heard is that you don't get into 300mm game without at least $10m, or better $20m if you have a brand new, untested design.
An expert? Ahahh, I never even had formal education in the field, just been trying to enter it, and start studies in it for a few years.
My only real experience with ICs was with a company developing a fancy synchronous rectifier chip what was capable of doing few more tricks with the output waveform besides rectification, and that was mostly just hanging around, and doing complete trivialities like routing, or minimal layout wiggling. I was more useful there as a coffee porter.
> How much do you estimate the full chip manufacturing cost for this would be ?
I don't know how many wafers they buy. I don't know whether they ordered masks from TSMC, or somebody else. I don't know how short they want lead times to be. I don't know if they want to have any device inspection provided. I don't know if they have any agreements on repeated runs, or a flexible capacity purchase. I don't know if they order test, and packaging from TSMC.
From a man who was on Allwinner's original A10 chip team, I heard that the most bare bones 65nm run without mask cost, inspection, or packaging was possible at 1k wafers at $2400-$2500 in 2013-2014 by paying cash 1y in advance.
Today, I'm not even sure if clients are even allowed to, or can order masks on the side these days for latest processes.
The universal advice I heard is that you don't get into 300mm game without at least $10m, or better $20m if you have a brand new, untested design.
The manufacturing cost is tiny. It's .2cm squared, so at 0.05 defects per cm^2, you expect to lose about 0.2% to defects. So-- die manufacturing costs are 2300/(20000*.996) == around 11 cents.
Small run packaging, along with distribution costs, etc, will dominate.
The real cost is amortization of R&D and mask costs.
Small run packaging, along with distribution costs, etc, will dominate.
The real cost is amortization of R&D and mask costs.
Don't forget software costs. Raspberry Pi foundation is known for excellent software and Pico seems to be intended that way too.
And that's money well spent, I think. If I'm a hobbyist and am planning on using a grand total of three microcontroller boards, than paying $2 x 3 for "blue pill boards", and then spending hours and hours debugging some obscure problem... that doesn't look like all that great of a deal, compared to paying $5 x 3 and making some use of polished examples and a nice build system:
https://github.com/raspberrypi/pico-examples
And that's money well spent, I think. If I'm a hobbyist and am planning on using a grand total of three microcontroller boards, than paying $2 x 3 for "blue pill boards", and then spending hours and hours debugging some obscure problem... that doesn't look like all that great of a deal, compared to paying $5 x 3 and making some use of polished examples and a nice build system:
https://github.com/raspberrypi/pico-examples
Here's a recent twitter thread you might like:
https://twitter.com/TubeTimeUS/status/1352676882920083457
https://twitter.com/TubeTimeUS/status/1352676882920083457
In the docs they described the naming convention for the processor, which suggests there are more under development
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The fab will eventually be upgraded. I design semiconductors and I have worked at two companies that had their own fabs (I didn't work in the fab)
Back in 1997 the new technology was 0.25 micron (250nm) but we still operated fabs at 0.35, 0.6, 0.8, and 1 micron. I believe these 4 lines operated at 6 different factories.
The next year we shut down the 1 micron fab. The building itself still had all the air filtering and cleanroom facilities. The old equipment (steppers, testers) was removed and new equipment for 0.18 micron was installed. I think this took about a year. At the end we still had 6 factories but the building that used to have all the old stuff was now the cutting edge fab.
Back in 1997 the new technology was 0.25 micron (250nm) but we still operated fabs at 0.35, 0.6, 0.8, and 1 micron. I believe these 4 lines operated at 6 different factories.
The next year we shut down the 1 micron fab. The building itself still had all the air filtering and cleanroom facilities. The old equipment (steppers, testers) was removed and new equipment for 0.18 micron was installed. I think this took about a year. At the end we still had 6 factories but the building that used to have all the old stuff was now the cutting edge fab.
What happens to the old equipment? Scrap?
Older processes available for cheap are not a new thing. They do indeed stay around until TSMC decide they're no longer worth running. It's not always cheaper as a larger process wastes more wafer.
I believe Eben Upton mentioned in a Twitter thread somewhere that they were getting thousands of chips off each wafer at the current node size? Only had to order like 20 or 40 wafers for the first production run, something like that.
Microelectronics cutting edge has been moving to smaller processes for the past 70 years. This is nothing new. If anything, the progress has slowed down.
Some fabs get closed down/rebuilt for a different process, some stay and produce parts that don't benefit from higher densities. Last I checked some ICs still get produced in 0.35 um processes. You don't need billions of transistors for an opamp.
Some fabs get closed down/rebuilt for a different process, some stay and produce parts that don't benefit from higher densities. Last I checked some ICs still get produced in 0.35 um processes. You don't need billions of transistors for an opamp.
I’d just like a documentary about fabs. It seems like an insane secret world of some of the most expensive places on earth. I’d love to know what they do with old ones etc.
This chip is very small and it does not benefit in any possible way from more advanced technological process. And using more advanced process means additional drawbacks and cost increases.
I think it is safe to say they will come out with a WiFi version. The 40nm will be beneficial then.
I really hope they do. I just bought a little ESP32 board, and while I'm having fun with it, it's a bummer that it's using an oddball ISA (xtensa). I really want to build for it in rust, but the xtensa llvm and rust forks are beta-ish quality, and there's no working wifi driver yet.
With the RP2040 based on ARM, rust should work on it after someone works up a peripheral support crate, which shouldn't be too hard if the RPi Foundation releases SVD files.
With the RP2040 based on ARM, rust should work on it after someone works up a peripheral support crate, which shouldn't be too hard if the RPi Foundation releases SVD files.
I don't understand this fascination with RP2040.
You want Rust to work on ARM? There is a huge selection of easy microcontrollers and boards.
Large boards, small boards, wifi, ethernet, usb, arduino compatible, anything you want.
https://www.st.com/en/ecosystems/stm32-nucleo.html
I have a bunch of these. I use them for prototyping before I put together a PCB design but they are fully functional if you want to build a product on them.
You want Rust to work on ARM? There is a huge selection of easy microcontrollers and boards.
Large boards, small boards, wifi, ethernet, usb, arduino compatible, anything you want.
https://www.st.com/en/ecosystems/stm32-nucleo.html
I have a bunch of these. I use them for prototyping before I put together a PCB design but they are fully functional if you want to build a product on them.
> how much of the older/larger capacity can be reused?
Not only reused, but expanded, and improved over the years.
So more than 100% of the original.
The biggest surprise of the last few years was the growth in really, really old 200mm fab capacity (late eighties, early nineties tech.)
Not only reused, but expanded, and improved over the years.
So more than 100% of the original.
The biggest surprise of the last few years was the growth in really, really old 200mm fab capacity (late eighties, early nineties tech.)
For how long is the equipment for these fabs amortized?
All eternity really. Even eighties era equipment is still being bought, and resold. Quite a number of early nineties fabs still work producing pretty much same things for 30 years straight.
Its easy to forget the long tail of smaller ICs these will get use out of for generations.
Not long, around five years after full production.
Oh wow this thread (and his whole Twitter account) is gold. thanks for sharing.
Edit: this zoomable image is great (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
Edit: this zoomable image is great (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
How does one of those die get made at all? It's such a minuscule small scale and it has such detail I cannot even comprehend how those components get "stamped" there, it's black magic.
Extremely simplified answer:
You know how a microscope makes a small image really big? You can also do the same in reverse -- take a big picture and project it really small. Use that idea to project your design on to your silicon, coated in a series of photosensitive chemicals that etch away the silicon until you have what you want.
You know how a microscope makes a small image really big? You can also do the same in reverse -- take a big picture and project it really small. Use that idea to project your design on to your silicon, coated in a series of photosensitive chemicals that etch away the silicon until you have what you want.
I like this animation showing how a FET is fabricated using photolithography processes: https://micro.magnet.fsu.edu/electromag/java/transistor/inde...
Thanks for sharing! It was really nice seeing each step of the process with a visualization.
A quick google for "homemade integrated circuit" brings up
http://sam.zeloof.xyz/first-ic/
At the very primitive end of the technology, integrated circuits can be made in the home workshop.
http://sam.zeloof.xyz/first-ic/
At the very primitive end of the technology, integrated circuits can be made in the home workshop.
It's not really "Stamped". It's more of a photographic process. My basic understanding is that they apply a photographic reactive chemical, expose it. From there they apply another chemical process to form an oxidation layer, and then use an acid process to "etch" away material creating channels of positively charged particles. Then they can apply a mask, and throw tiny amounts of metal which will become the gate.
The process of photolithography [1] involves a lot of complex optics, and interestingly you find a lot of lens manufacturers involved in it since it involves a lot of steps where light (e.g. lasers in this case) gets passed through a set of very precise optics until it hits the wafer and etches in the correct pattern from a larger 'reference copy'.
[1] https://en.wikipedia.org/wiki/Photolithography
[1] https://en.wikipedia.org/wiki/Photolithography
Actually, the process of actually "stamping" ICs mechanically is being pursued to make IC production even more cheaper.
https://en.m.wikipedia.org/wiki/Nanoimprint_lithography
https://en.m.wikipedia.org/wiki/Nanoimprint_lithography
From my partner who used to work at a fabless semiconductor:
The chipmaking process starts with code. Veralog I think is still being used. https://en.wikipedia.org/wiki/Verilog
You get information from your fab (libraries about sizes of things so you can do layouts and simulation with very expensive software (https://www.synopsys.com) (fun exercise, try to get a price on their website...)
Often you send your design to the fab to get some samples to test back.
Wikipedia has a decent summary about how the chips are made
https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...
The chipmaking process starts with code. Veralog I think is still being used. https://en.wikipedia.org/wiki/Verilog
You get information from your fab (libraries about sizes of things so you can do layouts and simulation with very expensive software (https://www.synopsys.com) (fun exercise, try to get a price on their website...)
Often you send your design to the fab to get some samples to test back.
Wikipedia has a decent summary about how the chips are made
https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...
It is "just" photo-etching, with the big wrinkle that 40nm is way below the wavelength of light, so all sorts of clever tricks with diffraction have to be done to make it work.
Take a watch of this: https://www.youtube.com/watch?v=NGFhc8R_uO4
The talk is a few years old, but that doesn't really matter because this chip was fabbed at 40 nm.
The talk is a few years old, but that doesn't really matter because this chip was fabbed at 40 nm.
I'm suprised that even the CPU cores are implemented just as a sea of standard cells. It is common to have them be macros containing a clearly separate datapath and control logic.
On the other hand, the fact that the prototyping was done on an FPGA makes this less surprising. Sea of cells is certainly easier to update, and less work than any form of manual datapath when migrating from FPGA to ASIC.
On the other hand, the fact that the prototyping was done on an FPGA makes this less surprising. Sea of cells is certainly easier to update, and less work than any form of manual datapath when migrating from FPGA to ASIC.
Yup. This is pretty clearly a case of getting it to run on an FPGA and using a commercial FPGA to ASIC service instead of spending a lot of time in synthesis and validation.
Mask costs can be cheaper this way, too, because some layers can be invariant between different parts.
Mask costs can be cheaper this way, too, because some layers can be invariant between different parts.
> using a commercial FPGA to ASIC service
This was not an FPGA conversion.
"Commercial FPGA to ASIC service" usually refers to Altera/Intel's HardCopy or Xilinx's EasyPath. EasyPath is where Xilinx sells you defective FPGAs for way cheaper, but with just enough of the right parts of the fabric working that your design can still fit and work properly. HardCopy is where Altera sells you a small number of metal mask layers to implement your design on a much smaller/faster sea-of-gates style ASIC that mimics the non-reprogrammable parts of the target FPGA.
The Raspberry Pi Foundation did neither of these things. They tested their design on an FPGA, which is common, and then used standard cell libraries and IP blocks provided by the fab and their partners to get through the normal ASIC workflow.
It turns out it's just easier and faster to tell the tools to automatically place and route the core complex than to do a careful floorplan. Also given that the RP2040 is apparently "very overclockable" (the PIO bitbanged HDMI output bumped the clock to something like double the nominally guaranteed maximum), the merits of doing it this way seem sound.
This was not an FPGA conversion.
"Commercial FPGA to ASIC service" usually refers to Altera/Intel's HardCopy or Xilinx's EasyPath. EasyPath is where Xilinx sells you defective FPGAs for way cheaper, but with just enough of the right parts of the fabric working that your design can still fit and work properly. HardCopy is where Altera sells you a small number of metal mask layers to implement your design on a much smaller/faster sea-of-gates style ASIC that mimics the non-reprogrammable parts of the target FPGA.
The Raspberry Pi Foundation did neither of these things. They tested their design on an FPGA, which is common, and then used standard cell libraries and IP blocks provided by the fab and their partners to get through the normal ASIC workflow.
It turns out it's just easier and faster to tell the tools to automatically place and route the core complex than to do a careful floorplan. Also given that the RP2040 is apparently "very overclockable" (the PIO bitbanged HDMI output bumped the clock to something like double the nominally guaranteed maximum), the merits of doing it this way seem sound.
> small number of metal mask layers to implement your design on a much smaller/faster sea-of-gates style ASIC
Ah, yes. The ULA. Whatever happened to those? Used to be a very promising way for small-(ish)-scale chip manufacturing.
https://en.wikipedia.org/wiki/Uncommitted_logic_array
Ah, yes. The ULA. Whatever happened to those? Used to be a very promising way for small-(ish)-scale chip manufacturing.
https://en.wikipedia.org/wiki/Uncommitted_logic_array
I think Eben even said they're planning to make 252mhz/1.2v an official clock speed soon...
He did! I was looking for the tweet so I could cite it, but wasn't able to find it.
Edit: Found it
https://twitter.com/EbenUpton/status/1352564580434792452
Edit: Found it
https://twitter.com/EbenUpton/status/1352564580434792452
Interestingly, there are documented bits in registers for marking whether you're running on an FPGA or as an ASIC.
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The resistor value captcha at the end of the page is golden.
How do I interact with it? I tried picking the colors, but nothing I tried did anything.
You can drag the slider. Clicking doesn't seem to work.
Doesn't work for me on Firefox.
I'm guessing it works on Chrome, but it also would sort of surprise me that a maker website wouldn't test against Firefox. Maybe I'm giving them too much credit.
I'm guessing it works on Chrome, but it also would sort of surprise me that a maker website wouldn't test against Firefox. Maybe I'm giving them too much credit.
It took me a minute to figure out, you have to drag the circle up and down to select the number. I had expected to drag the whole bar - oops!
Edit: Also on FF. (85.0 on Linux)
Edit: Also on FF. (85.0 on Linux)
Strange. I'm on Firefox and it works for me.
One of my regrets from when I worked at Intel was that we had die plans on 36x48 printouts in the lab - and they were beautiful, I wish I had taken them home - I would love to have some framed on my walls now.
A simple stack of these images with a CSS offset (to give it a 3-d look) would be great.
Edit: his zoomable image is even better (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
Edit: his zoomable image is even better (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
How do you change the layer?
If you navigate up one directory, there are a couple more layers available: https://siliconpr0n.org/map/raspberry-pi/rp2-b0/
My pair arrived last Friday. With bare metal coding I have its LED blinking. Now I'm just thinking how to bring up a very small SMP capable UNIX clone in it. If the PDP/11 could do it I see no reason why it can't be done on the Pico.
Fuzix exists for 6502 and Z80 processors and these are tiny!
Fuzix exists for 6502 and Z80 processors and these are tiny!
Not a big fan of Twitter but I have to say it was an amazing use of the medium.
How common is it to use copper bondwires? I thought these were always gold.
Interesting. I did not realize wire bonding is still used on large devices.
cheap microcontrollers:
ESP32: WiFI, no USB
RP2040: USB, no WiFi
:(
ESP32: WiFI, no USB
RP2040: USB, no WiFi
:(
ESP32-S2 has both WiFi and USB. It's essentially (the classic) ESP32 cut to a single core, 320KB RAM, and with Bluetooth removed; however it does include USB.
There's also ESP32-S3 which is dual core, with more RAM, USB, and Bluetooth, but I'm not sure any boards are available yet.
All of that not to be confused with ESP32-C3 which is a single-core RISC-V without USB.
And yes, their naming is confusing.
edit: Adafruit has some boards with ESP32-S2. If you get a random board from elsewhere, there are good chances it will come with a USB-to-serial chip, which you don't want if you need to use native USB. So check.
There's also ESP32-S3 which is dual core, with more RAM, USB, and Bluetooth, but I'm not sure any boards are available yet.
All of that not to be confused with ESP32-C3 which is a single-core RISC-V without USB.
And yes, their naming is confusing.
edit: Adafruit has some boards with ESP32-S2. If you get a random board from elsewhere, there are good chances it will come with a USB-to-serial chip, which you don't want if you need to use native USB. So check.
> ESP32-S2 has both WiFi and USB
USB 1.0/1.1 right? Not 2.0?
USB 1.0/1.1 right? Not 2.0?
The "Arduino Nano RP2040 Connect" is an RP4040 board slated to be coming soon that will provide WiFi and Bluetooth.
I expect we'll see more RP2040 devboards & SOMs coming soon that fill the connectivity niche.
I expect we'll see more RP2040 devboards & SOMs coming soon that fill the connectivity niche.
Bluetooth? I’m looking for WiFi + USB.
Alternative Twitter thread: https://twitter.com/johndmcmaster/status/1355092011829719046
Yes, much better, thank you. (I made the same suggestion)
Ok, we'll change to that from https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspbe.... Thanks!
Why not link to the original thread instead?
https://twitter.com/johndmcmaster/status/1355092011829719046
https://twitter.com/johndmcmaster/status/1355092011829719046
Changed from https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspbe.... Thanks!
Attention to detail is amazing!
I wonder, with the cutting edge moving to smaller and smaller processes (5nm, etc)... how much of the older/larger capacity can be reused? Meaning, are we about to see a ton of cheaper chips like this RP2040 that are using older/slower/obsolete fab capacity? Or is the same equipment able to be used across a family of process sizes?
In other words, once TSMC has X amount of capacity on 40nm, is that capacity always around and fixed to 40nm? If so, I imagine that creating new chips that don't need to be super fast will just become super cheap.