Verilog to Minecraft Redstone Synthesizer(github.com)
github.com
Verilog to Minecraft Redstone Synthesizer
https://github.com/itsFrank/MinecraftHDL
4 comments
Not sure if it would be suitable for a 10yo, but check out MHRD (on steam or itch.io), you start out with NAND gates and gradually build more complex constructs that you reuse in the following levels, where the final level is a (very simple) CPU. Sort of like the first few parts of Nand2Tetris.
It uses a very simple HDL, has a reasonable IDE built in, and each puzzle is pass/fail based on a test suite so it's easy to get into - however, you only have a certain number of lines on screen in which to write the HDL (and comments), so brute force is not an option for most of the puzzles, you do have to optimise your design to fit the constraints.
It uses a very simple HDL, has a reasonable IDE built in, and each puzzle is pass/fail based on a test suite so it's easy to get into - however, you only have a certain number of lines on screen in which to write the HDL (and comments), so brute force is not an option for most of the puzzles, you do have to optimise your design to fit the constraints.
I second this, MHRD was a very good intro for me
You can also just let him play with redstone and once he got the hang of the elementary gates then let him play nandgame.
Can confirm, nandgame was a hit with my 12-year-old.
While it may produce the right logic tables, there's a lot of room for optimisation. I'd like to see that. For instance the two repeaters near the end of the 4th trace from bottom in the example image []: obviously they have just been placed at element boundaries to ensure signal propagation, but each one induces a 1-tick delay in that propagation. And you don't need 2 of them so close together, as it seems there's another repeater less than 16 blocks away from the first one. IMO the real art of making gates in MC is twisting them back on themselves so you get as few ticks of delay as possible.
[] https://raw.githubusercontent.com/itsFrank/MinecraftHDL/mast...
[] https://raw.githubusercontent.com/itsFrank/MinecraftHDL/mast...
This is so Greg Egan.
(An Australian sci-fi author who likes to layer realities computed/simulated on top of each other - give Diaspora or Permutation City if it sounds like your cup of tea.)
(An Australian sci-fi author who likes to layer realities computed/simulated on top of each other - give Diaspora or Permutation City if it sounds like your cup of tea.)
Speaking of Greg Egan. Is it just me, or is the ending of Diaspora somewhat anticlimactic? There are so many interesting ideas he touches upon without exploring them in depth and then the narrative loses steam and dies of.
I don't think the ending was intended to act as a climax to the narrative. Rather, it's the logical conclusion of several ideas shown earlier in the story; modifications to how you think that can't be reversed; alien consciousnesses that you can never actually communicate with; the logical conclusion of the original quest to prolong humanity's simulated existence, which is why they go exploring in the first place.
I wonder if it's just common to have many unexplored ideas and unfinished side stories?
I recall Accelerando also had many of these, probably A Deepness in the Sky as well (though I don't recall it in detail anymore).
Or maybe I just recall noticing that detail and forget about the ones where I didn't notice it.
Or maybe I just recall noticing that detail and forget about the ones where I didn't notice it.
That was absolutely my feeling as well.
See also: https://github.com/google/minetest_pnr
Similar project but for minetest (open source minecraft clone)
Similar project but for minetest (open source minecraft clone)
In his case I suspect the full syntax of Verilog would be overkill and just add confusion, though. A simpler subset without modules and with only continuous assignment would be ideal.
Gears turning.