The Tyranny of the Clock (2012) [pdf](eng.auburn.edu)
eng.auburn.edu
The Tyranny of the Clock (2012) [pdf]
http://www.eng.auburn.edu/~uguin/teaching/READING/E6200/Sutherland_Tyranny_o_Clock.pdf
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Related talk by the author (Ivan Sutherland): https://www.youtube.com/watch?v=jR9pAaQlVRc
When I read the title I was reminded of this
https://youtu.be/tVT2Xi1kwx0
https://youtu.be/tVT2Xi1kwx0
in verilog there is a distinction between asynchronous
combinatorial logic and synchronous sequential logic
wires are treated as transmission lines
wires are treated as transmission lines
http://arc.cecs.pdx.edu/publications