Yep, and the highest data rates are only really possible on the best processes (12nm, 7nm, 5nm) , which is a fun chunk of change to spend for a tape out.
Think of this product as infrastructure-as-code for the Silicon/ASIC workflow. It's a pythonic API for the ASIC/VLSI workflow as opposed to the traditional spaghetti script TCL nightmare that holds together modern ASIC flows.
Though they are essentially given for free, stitching everything together is still a lot of work. Getting the tools as an individual is not really possible (with the exception of Mentor sometimes..) the open source software ecosystem needed around every tool is non-existent, which means that each company ends up recreating their own scripts and flows each time you want to design a new IP.
I've kind of always felt that synthesizable Verilog/SystemVerilog was good, but the verification side was just too complex and had too much bloat. Testing hardware with Python (like Cocotb) feels more on the right track as a high level UI.
But easily pluggable APIs for foreign SW languages are key as well. Hardware software co-design is only becoming more important.
Higher level hardware design languages that better interop with software are desperately needed, but I don't know if C/C++ is the right UI/abstraction.
I want my private keys stored on my iPhone / Apple Watch, in Secure Enclave memory, with two-factor biometric authentication (FaceID and Fingerprint). No more passwords.
Awesome. I guess two comments on learn-anything -- is there an easy way for external users to add something? I get it's open source but when you search for something, maybe a "suggest resource" would speed up curation of resources via human indexing.
The other big thing that would be helpful is a "videos" node where you could link to videos on the subject. A lot of people that I talk to struggle learning completely new topics just by reading. Some of the feedback I hear is that a few videos goes a long way to introducing something new, so a videos node could be useful in the overall graph.